Coating processes – Electrical product produced – Integrated circuit – printed circuit – or circuit board
Reexamination Certificate
2000-01-20
2003-04-29
Barr, Michael (Department: 1762)
Coating processes
Electrical product produced
Integrated circuit, printed circuit, or circuit board
C427S098300, C427S230000, C427S240000, C427S304000, C427S305000, C427S383100, C427S437000, C427S438000, C427S443100
Reexamination Certificate
active
06555158
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for plating, and a plating structure and for example, to a method and apparatus that are preferable for forming a copper interconnection in a contact hole or an interconnect trench, and an interconnect structure in a semiconductor integrated device.
BACKGROUND OF THE INVENTION
Al (aluminum) interconnects have conventionally been formed in fine contact holes or interconnect trenches of a high density integrated circuit fabricated on a semiconductor wafer (hereinafter referred to as wafer). The Al interconnects, however, have exposed a tendency to be increasingly replaced with Cu (copper) interconnects because of its limited resistance to electromigration. As Cu interconnection techniques in the contact holes and interconnect trenches, a so called Damascene approach that comprises a process in which Cu interconnection material is filled into the openings by electroplating and unnecessary portions of the interconnection material are removed by polishing using a CMP (Chemical Mechanical Polishing) technique has been regarded as having great promise in the future for reduction in manufacturing cost of a semiconductor device since there is no need to fill spaces between interconnects with an interlayer insulating film. Further, an interconnect can be formed in an opening with a high aspect ratio.
FIGS. 1
to
4
are sectional views schematically showing a copper interconnection process by means of a Damascene technique (here, a dual Damascene technique).
That is, in the process shown in the figures, insulating layers
34
and
35
, such as layers made of SiO
2
, are stacked on copper interconnects
32
a
and
32
b
(on whose upper and lower surface barrier layers
33
are provided) which are formed on a wafer
31
by etching or the like. Thereafter, a contact hole
36
and interconnect trenches
37
are formed by etching or the like and copper interconnects are formed by electroplating copper which constitutes as interconnection material. In the interconnection process, a seed layer
39
that serves as nuclei for plating is formed in the contact hole
36
and interconnect trench
37
as shown in
FIG. 2
after a barrier layer
38
is formed as shown in FIG.
1
. Following formation of the seed layer, a copper electroplating layer
40
is formed as shown in
FIG. 3
(which is an enlarged sectional view of a region in the vicinity of the contact hole
36
of
FIG. 2
) and the electroplating layer
40
is polished off to form an copper interconnect
43
in the contact hole
36
as shown in FIG.
4
. In addition, a copper interconnect similar to that in the contact hole
36
is simultaneously formed in the interconnect trench
37
as well.
However, a recess
42
and a seam
41
are apt to occur respectively on and in the interconnect as shown in the figures. Associated with this phenomenon, there arise problems such as items (1) to (4) which will be shown as follows: (1) Since an electroplating film is deposited on the surface of the wafer
31
and, especially, in the vicinity of the mouth of the blind hole (contact hole)
36
with priority assigned thereto, there arise limitations that the minimum of a diameter D of the blind hole
36
is 0.25 &mgr;m and the highest aspect ratio thereof is of the order of 5. (2) Filling by electroplating into the blind hole
36
is possible by selecting an effective combination of additives. However, when the additives are selectively combined so as to electroplate a small diameter blind hole, an almost flat surface finish is obtained in a wide mouthed trench, whereas a swollen surface finish is formed at the top of a small diameter blind hole; that is, a flat surface finish is hard to acquire in a small diameter blind hole, which entails more difficulty in planarization by CMP. (3) As shown in
FIG. 2
, when the seed layer
39
is formed, the seed layer
39
is not formed on the sidewall of the blind hole
36
in a uniform thickness, but rather the layer
39
is apt to be formed thick on the upper surface and areas in the vicinity of the respective mouths of the blind hole
39
and interconnect trench
37
. Such spatial thickness distribution of the seed layer
39
with a large dispersion, in turn, is a cause for a spatial thickness dispersion in electroplating. (4) Further, when electroplating is performed in an apparatus of a rotary electrode type, a thickness variation along a diameter is recognized: the state is such that an 8 inch diameter wafer has a variation of the order of 3% and a 12 inch diameter wafer has a variation of the order of 5%, which acts as a difficult factor in globally uniform planarization across the entire surface of a wafer.
OBJECTS AND SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a method and apparatus for plating with high productivity by means of which plating an interconnection with uniformity, high quality and high planarity can be achieved even in a hole with a high aspect ratio and over a large area plating region, and a plating structure.
According to one aspect of the present invention , there is provided a method for plating in which at least a hole is plated with a metal, comprising: a first step of removing organic material existent in a plating region; a second step of hydrophilizing a surface of the plating region after the first step; a third step of bonding a coupling agent with the surface hydrophilized by the second step; a fourth step of bonding a catalytic metal with the coupling agent at the surface after the third step; a fifth step of exposing the catalytic metal to activate after the fourth step; and a sixth step of electrolessly plating the activated surface after the fifth step.
According to a method for plating of the present invention, when at least a hole, such as a blind hole, is plated as a plating region, since organic material existent in a plating region is removed and the surface is hydrophilized, further a catalytic metal is bonded with a coupling agent that is bonded with the surface, and the surface is exposed, activated and then electrolessly plated, plating is effected uniformly at the mouth, bottom and sidewall of the hole and further no seed layer is required, which is different from a conventional electroplating. Hence, not only a flat surface but a hole with a high aspect ratio can be plated in a uniform manner with a good quality and in addition, a plating layer with high flatness can be formed at the top part of the hole. Therefore, polishing following the plating is easy to be effected and electroless plating can be conducted directly after the polishing without either physical surface roughening or a heat treatment (see JP 93-101974 A), thereby enabling a method for plating with high productivity to be provided.
According to another aspect of the present invention, there is provided an apparatus for plating in which at least a hole is plated with a metal, comprising: a pretreatment section which performs a first step of removing organic material existent in a plating region, a second step of hydrophilizing a surface of the plating region after the first step, a third step of bonding a coupling agent with the surface hydrophilized by the second step, a fourth step of bonding a catalytic metal with the coupling agent at the surface after the third step, and a fifth step of exposing the catalytic metal to activate after the fourth step; and an electroless plating section which performs a sixth step of electrolessly plating the activated surface after the fifth step. According to the present invention, there can be provided an apparatus for electroless plating with good reproducibility since the apparatus is based on the above described method for plating, which apparatus comprises the pretreatment section and electroless plating section.
According to still another aspect of the present invention, there is provided a plating structure that is formed by plating at least a hole with a metal, wherein a coupling agent is bonded with a hydroxylated surface of a pla
Segawa Yuji
Yoshio Akira
Barr Michael
Kananen, Esq. Ronald P.
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