Method and apparatus for placing and detecting prewire blockages

Details Method and apparatus for placing and detecting prewire blockages Method and apparatus for placing and detecting prewire blockages

1995-12-21

1998-08-11

Trammell, James P.

Boots, shoes, and leggings

364489, 364490, 364491, G06F 1500

Patent

active

057936412

ABSTRACT:
A method and apparatus for detecting valid placement of library cells on chip images or hierarchy design images may be accomplished by determining a periodic pattern of the chip image, or hierarchical image. Once the repetitive pattern is recognized, this pattern is represented by a binary vector. Similarly, a binary vector is created for a particular cell library that is to be placed on the chip image or hierarchical design image. When the placement algorithm places the library cell on the chip or hierarchical image, the binary vector of the library cell is folded over a folded binary vector of the chip image or hierarchical design image to produce a component delta set. In essence, the component delta set indicates spacing violations between the library cell and the chip or hierarchical design image. When such a spacing violation is recognized, the placement algorithm can immediately reposition the library cell.

REFERENCES:
patent: 5483461 (1996-01-01), Lee et al.
patent: 5587923 (1996-12-01), Wang

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