Method and apparatus for pipelining cache accesses using anticip

Details Method and apparatus for pipelining cache accesses using anticip Method and apparatus for pipelining cache accesses using anticip

1989-11-13

1993-10-12

Gossage, Glenn

Boots, shoes, and leggings

395550, 3642384, 36424341, 3642318, 36494834, 36496426, 364968, 365233, G06F 1300

Patent

active

052533522

ABSTRACT:
A high speed memory component, such as a cache RAM (random access memory), has a bidirectional data line and a control line (CDRAMOE) which, when respectively set to first and second electrical states, causes the memory component to respectively output data onto and accept data from the bidirectional data line. An arrangement is provided to initiate transfers of data to and from the memory component on the bidirectional data line and to produce at a first point in time a valid indication signal (W/R) indicating that one of a data read and a data write is being initiated. A method and apparatus for controlling the memory component involve the control line being set to the second electrical state at a second point in time prior to the first point in time, and the control line being maintained in the second electrical state from the second point in time to the first point in time.

REFERENCES:
patent: 4872138 (1989-10-01), Ciacci

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