Patent
1997-08-26
1998-08-18
Shin, Christopher B.
395840, 395856, 395868, 395733, 395281, G06F 1300
Patent
active
057970319
ABSTRACT:
A digital data processor has a central processing unit (CPU) that operates in plural addressing modes and or more adapters for receiving peripheral devices, e.g., PCMCIA devices. A first peripheral device service subsystem that handles communications between peripheral devices coupled to the adapters and software clients executing on the CPU in a first addressing mode. A second peripheral device service subsystem that handles communications between peripheral devices coupled to the adapters and clients executing on the CPU in a second addressing mode. The first peripheral device subsystem includes a configuration management section that allocates digital data processor resources, e.g., memory space, input/output channels, direct memory access (DMA) channels and interrupt (IRQ) levels, used for communications between the peripheral devices and clients, regardless of whether those clients are executing in the first or second addressing modes.
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Schumacher Steven
Shapiro Raymond E.
Stanley Paul C.
Shin Christopher B.
SystemSoft Corporation
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