Method and apparatus for performing serial and parallel scan tes

Details Method and apparatus for performing serial and parallel scan tes Method and apparatus for performing serial and parallel scan tes

1995-11-30

1997-02-25

Canney, Vincent P.

Excavating

371 223, G06F 1100

Patent

active

056065680

ABSTRACT:
An integrated circuit test apparatus according to an exemplary embodiment includes a first memory section configured to store processor procedures and a second memory section configured to simultaneously store parallel integrated circuit test vectors and serial integrated circuit test vectors. A processor is coupled to the first memory section and to the second memory section. The processor is configured to execute the processor procedures to simultaneously manipulate the parallel integrated circuit test vectors and the serial integrated circuit test vectors located in the second memory to test an integrated circuit. Advantages of the invention include the ability to simultaneously store serial and parallel test vectors and to test a device under test (DUT) with simultaneous serial and parallel test vectors. The combination of serial and parallel test vectors increases performance and efficiency of the test apparatus.

REFERENCES:
patent: 5483544 (1976-01-01), Shur

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