Method and apparatus for performing restricted modulo arithmetic

Details Method and apparatus for performing restricted modulo arithmetic Method and apparatus for performing restricted modulo arithmetic

1990-11-26

1993-09-28

Smith, Jerry

Boots, shoes, and leggings

G06F 738

Patent

active

052491480

ABSTRACT:
A digital data processor is capable of performing limited modulo arithmetic. The base, M, of the modulo arithmetic to be preformed by the processor must be equal to 2.sup.X, where X is an integer. The method and apparatus is particularly useful for generating addresses for a circular buffer or queue data structure and avoids both the large amount of hardware required for general modulo arithmetic and the software overhead associated with the use of linear arithmetic to generate modulo addresses. According to this method, X is represented as a first digital value. This representation of X is ANDed with a second digital data value (an offset). The result is then ADDed linearly with a third digital data value (a current address with the buffer). During this addition process, certain carry-out signals are inhibited from propagating, according to the digital representation of X.

REFERENCES:
patent: 4187549 (1980-02-01), Bond et al.
patent: 4722067 (1988-01-01), Williams
patent: 4742479 (1988-05-01), Kloker et al.

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