Electrical computers and digital processing systems: multicomput – Computer-to-computer protocol implementing – Computer-to-computer data streaming
Reexamination Certificate
1996-09-12
2001-04-03
Burgess, Glenton B. (Department: 2153)
Electrical computers and digital processing systems: multicomput
Computer-to-computer protocol implementing
Computer-to-computer data streaming
Reexamination Certificate
active
06212567
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to an end node in a high performance computer system or network, such as an ATM network, and more particularly, to a method and apparatus for improving the performance level of the end node by reducing system overhead and maximizing bus bandwidth utilization.
BACKGROUND OF THE INVENTION
A large part of the cost of networking is the cost of moving data between a host computer system and a network. Under conventional approaches, systems buffer network data in host memory buffers, which are sometimes chained into linked lists. Buffer chaining is typically employed in systems utilizing “scatter-gather” techniques. For example, when the host system needs to transmit a data packet stored in buffers to a network via a network interface or adapter, it makes available to the network adapter control information associated with each buffer. The control information may include, among other buffer-related information, a pointer to a buffer of data and the length of the buffer. The chain of buffers is passed to the appropriate host system protocol stack, where the chain is augmented with the appropriate headers, and subsequently, to the driver for transmission. The driver then instructs the network adapter to copy the buffer data into the network interface's local memory and transmit the packet onto the network. The adapter must then parse the linked lists in gathering the various host memory buffers associated with the packet to be transmitted and copy the buffers into the local memory. One known technique for copying the buffer data from host memory to network adapter local memory without involving the host CPU is direct memory access (DMA).
In an alternative approach, commonly referred to as “programmed I/O”, the data copying is performed by the host CPU. During a transmit operation, the host CPU reads the address of an available adapter transmit buffer, writes the available transmit buffer with packet header and application data, and then writes the associated control information into a buffer. Once the adapter transmits the packet data onto the network, the freed buffer address is placed back in the transmit buffer and is returned to the host CPU. A receive operation functions in a similar manner. Incoming packets are queued in a receive buffer. Upon receiving an interrupt, the host CPU reads the buffer address and the contents of the buffer corresponding to the address, and subsequently returns the buffer address to the adapter to be re-used.
Because the system bus must be utilized in every host-adapter operation performed by a computer system, its characteristics and utilization have a major impact on the overall performance of the system. It can be observed that, in the aforementioned system implementations, control communications as well as data transfers take the form of both read and write transactions. Because of the added latencies associated with read access times (i.e., turnaround address-to-data time), a high ratio of read transactions to write transactions can adversely impact system bus and therefore overall system performance. Bus performance is further degraded by the number of control transactions, since control transactions consume bus bandwidth, thereby reducing the bandwidth available for data movement. Both transmit and receive throughput is adversely affected by lower levels of system bus bandwidth availability and high control/data overhead; consequently, the overall throughput rate is lower. The impact of control transactions becomes even more pronounced in systems transmitting and receiving a great number of smaller packets, because of the higher control/data overhead associated with such smaller packets. Thus, it can be seen that control communications, and more specifically, control read transactions, do not make efficient use of the system bus.
Another problem encountered in high performance systems, and more specifically, those high performance systems which employ a burst mode type of system or local bus, is the inability to burst write data to a single location, such as a data FIFO. Burst mode buses, such as the PCI bus, do not allow a burst access to a single address location. Instead, the accesses must appear on the bus as separate and distinct transactions. Again, overall performance suffers.
System performance can also be adversely affected by other host-adapter interactions, such as interrupts and reporting operations. Interrupts occur when a device like a network interface signals the host to indicate that the device needs to be serviced. In a typical network interface application, the host may be interrupted for a variety of reasons. For example, the adapter may generate an interrupt and a report to the host when a data packet to be transmitted has been transferred by a DMA operation from host memory to adapter local memory. An interrupt and report may also occur when an incoming data packet has been transferred from the adapter to the host memory. The cost of such interactions can be significant. Moreover, in the case of smaller packets or cells, such as ATM raw cells, for which little data copying is done, these other interactions often represent most of the cost of sending a packet. Thus, it may be undesirable to report status and interrupt the host on a per-cell basis.
Therefore, there exists a clearly felt need in the art for a mechanism which provides for high bus bandwidth utilization and low-latency control communications between a host computer and a high performance peripheral, such as an ATM network adapter. Further, there is a need to suppress or minimize the frequency of interrupt requests and reports queued to the host system.
SUMMARY OF THE INVENTION
Accordingly, there is provided a method and corresponding apparatus for mitigating the frequency with which status reports associated with raw cell data transfers occur during receive operations in a network node. The network node has a network and a host system including a host memory coupled to the network by an adapter. The adapter reassembles cell data received from the network and stores the reassembled cell data in the host memory. The method of the present invention begins by programming a raw report holdoff counter to count a number corresponding to a preselected rx raw report holdoff value. If a raw cell data transfer request to be processed is detected, rx raw report information necessary to creating an rx raw cell status report is copied to a temporary storage area. The method performs the data transfer of the raw cell data to the host system and modifies the raw report holdoff counter by one. If the modified counter has expired (i.e., counted a number corresponding to a preselected rx raw report holdoff value), the rx raw report information is written to a report queue in host memory and the raw report holdoff counter is reloaded. If the modified raw report holdoff counter has not expired, then the method returns to the step of detecting a raw cell data transfer request to be processed.
REFERENCES:
patent: 5249271 (1993-09-01), Hopkinson et al.
patent: 5450546 (1995-09-01), Krakirian
patent: 5623494 (1997-04-01), Rostoker et al.
patent: 5633870 (1997-05-01), Gaytan et al.
patent: 5650993 (1997-07-01), Lakshman et al.
patent: 5680401 (1997-10-01), Gayton et al.
patent: 5694390 (1997-12-01), Yamato et al.
patent: 5717932 (1998-02-01), Szczepanek et al.
patent: 5740468 (1998-04-01), Hirose
patent: 5870628 (1999-02-01), Chen et al.
Cheung Wing
Roman Peter J.
Thomas Robert E.
Washabaugh Douglas M.
Burgess Glenton B.
Compaq Computer Corporation
Hamilton Brook Smith & Reynolds P.C.
Kupstas Tod
LandOfFree
Method and apparatus for performing raw cell status report... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for performing raw cell status report..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for performing raw cell status report... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2463819