Method and apparatus for performing pipeline store instructions

Details Method and apparatus for performing pipeline store instructions Method and apparatus for performing pipeline store instructions

1996-06-20

1998-02-10

Kim, Matthew M.

395403, 395381, G06F 1208

Patent

active

057178968

ABSTRACT:
A mechanism for implementing a store instruction so that a single cache access stage is required. Since a load instruction requires a single cache access stage, in which a cache read occur, both the store and load instructions of the present invention utilize a uniform number of cache access stages. The store instruction is implemented in a pipeline microprocessor such that during the pipeline stages of a given store instruction, the cache memory is read and there is an immediate determination if there is a tag hit for the store. Assuming there is cache hit, the cache write associated with the given store instruction is implemented during the same pipeline stage as the cache access stage of a subsequent instruction that does not write to the cache or if there is no instruction. For example, a cache data write occurs for the given store simultaneously with the cache tag read of a subsequent store instruction. This allows for a more uniform and efficient pipeline format for each instruction. During the period in which a given store is delayed, its data is placed into a store buffer. On a cache miss, when a data line returns from memory, the store buffer locates a free period of the cache and stores the data. The store mechanism is implemented in a pipeline processor and also with a general purpose computer system.

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