Patent
1995-06-06
1997-06-03
Treat, William M.
395384, 395568, G06F 930
Patent
active
056363745
ABSTRACT:
In a microprocessor, an apparatus and method for performing memory functions and issuing bus cycles. Special microinstructions are stored in microcode ROM. These microinstructions are used to perform the memory functions and to generate the special bus cycles. Initially, an address corresponding to a requested operation to be performed is generated for one of these special microinstructions. That special microinstruction, along with its address, is then transmitted over the bus to the various units of the microprocessor. When each of the units receives the microinstruction, it determines whether that microinstruction is to be ignored based on the address. If a particular unit ignores the microinstruction, the microinstruction is forwarded to subsequent units in the pipeline for processing. Otherwise, if that particular unit performs the requested operation as specified by the microinstruction's address.
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Akkary Haitham
Brayton James A.
Glew Andrew F.
Karnik Milind A.
Konigsfeld Kris G.
Intel Corporation
Treat William M.
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