Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Patent
1997-03-24
2000-01-11
Mai, Tan V.
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
708625, G06F 752
Patent
active
060146842
ABSTRACT:
A method and apparatus for performing N bit by 2*N (or 2*N-1) bit signed multiplication using two N bit multiply instructions. According to one aspect of the invention, a method for performing signed multiplication of A times B (where B has N bits and A has N*2 bits) is described. In this method, A.sub.high and A.sub.low respectively represent the most and least significant halves of A. According to this method, A.sub.low is logically shifted right by one bit to generate A.sub.low >>1. Then, A.sub.low >>1 is multiplied by B using signed multiplication to generate a first partial result. In addition, a second partial result is generated by performing signed multiplication of A.sub.high times B. One or both of the first and second partial results is shifted to align the first and second partial results for addition, and then the addition is performed to generate a final result representing A multiplied by B.
REFERENCES:
patent: 3711692 (1973-01-01), Batcher
patent: 3723715 (1973-03-01), Chen et al.
patent: 4161784 (1979-07-01), Cushing et al.
patent: 4393468 (1983-07-01), New
patent: 4418383 (1983-11-01), Doyle et al.
patent: 4498177 (1985-02-01), Larson
patent: 4707800 (1987-11-01), Montrone et al.
patent: 4771379 (1988-09-01), Ando et al.
patent: 4989168 (1991-01-01), Kuroda et al.
patent: 5095457 (1992-03-01), Jeong
patent: 5187679 (1993-02-01), Vassiliadis et al.
patent: 5586070 (1996-12-01), Purcell
patent: 5880985 (1999-03-01), Makineni et al.
J. Shipnes, Graphics Processing with the 88110 RISC Microprocessor, IEEE (1992), pp. 169-174.
MC88110 Second Generation RISC Microprocessor User's Manual, Motorola Inc. (1991).
Errata to MC88110 Second Generation RISC Microprocessor User's Manual, Motorola Inc. (1992), pp. 1-11.
MC88110 Programmer's Reference Guide, Motorola Inc. (1992), p. 1-4.
i86Q.TM. Microprocessor Family Programmer's Reference Manual, Intel Corporation (1992), Ch. 1, 3, 8, 12.
R. B. Lee, Accelerating Multimedia With Enhanced Microprocessors, IEEE Micro (Apr. 1995), pp. 22-32.
TMS320C2x User's Guide, Texas Instruments (1993) pp. 3-2 through 3-11; 3-28 through 3-34; 4-1 through 4-22; 4-41; 4-103; 4-119 through 4-120; 4-122; 4-150 through 4-151.
L. Gwennap, New PA-RISC Processor Decodes MPEG Video, Microprocessor Report (Jan. 1994), pp. 16, 17.
SPARC Technology Business, UltraSPARC Multimedia Capabilities On-Chip Support for Real-Time Video and Advanced Graphics, Sun Microsystems (Sep. 1994).
Y. Kawakami et al., LSI Applications: A Single-Chip Digital Signal Processor for Voiceband Applications, Solid State Circuits Conference, Digest of Technical Papers; IEEE International (1980).
B. Case, Philips Hopes to Displace DSPs with VLIW, Microprocessor Report (Dec. 94), pp. 12-15.
L. Gwennap, UltraSparc Adds Multimedia Instructions, Microprocessor Report (Dec. 94), pp. 16-18.
N. Margulis, i860 Microprocessor Architecture, McGraw Hill, Inc. (1990) Ch. 6, 7, 8, 10, 11.
Pentium Processor User's Manual, vol. 3; Architecture and Programming Manaual, Intel Corporation (1993), Ch. 1, 3, 4, 6, 8,and 18.
Intel Architecture MMX.TM. Technology Programmer's Reference Manual, Legal Stuff.COPYRGT. 1997 Intel Corporation (Mar. 1996).
MMX.TM. Technology Developers Guide, Legal Stuff.COPYRGT. 1997 Intel Corporation. MMX.TM. Technology Technical Overview, 1996 Intel Corporation.
Foley, van Dam, Feiner and Hughes, Computer Graphics--Principles and Practice (1996), Addison-Wesley Publishing Co. Inc., pp. 213-217.
MMX.TM. Technology Application Note, Using MMX Instructions to Perform 16-Bit.times.31-Bit Multiplication, 1996 Intel Corporation, 6 pages.
MMX.TM. Technology Application Note, Using MMX Instructions to Perform 3D Geometry Transformations, 1996 Intel Corporation, 20 pages.
Intel Corporation
Mai Tan V.
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