Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Reexamination Certificate
1999-09-08
2003-03-11
Mai, Tan V. (Department: 2124)
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
Reexamination Certificate
active
06532485
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to combination multiplication and addition operations in a computing environment. More particularly, the present invention relates to an apparatus for performing nonparallel and parallel multiplication/addition operations, and a method for operating that apparatus.
2. The Background Art
In modern computers, there exists a mathematical function N=A*B+C which is performed frequently. Although the entire function is important, the prior art performs the multiplication first, and then adds “C” to the result.
Two types of methods are used commonly in computers to perform the multiplication/addition calculation, parallel and traditional.
Traditional multiplication divides the two numbers into upper and lower halves. The upper and lower halves are then multiplied together in succession, and the results of those multiplications are then added together, forming the final result of the multiplication.
Therefore, two 32-bit numbers “A” and “B” being multiplied together will each be broken into halves, making “Ah” and “Al” represent the upper and lower halves of the number “A”, and “Bh” and “Bl” represent the upper and lower halves of the number “B”. The functions Ah*Bh+Ch=Nh, and Al*Bl+Cl=Nl are then performed, and the two results Nh and Nl are then put back together as [Nh] [Nl] to form the final result N. This method of combining three numbers requires 2 identical apparatus's, each operating in parallel on different halves of the calculation.
Parallel multiplication, the second method, takes the same numbers “A”, “B” and “C” and also breaks each of them into upper and lower halves. The lower half of each is sign extended to the size of the original number. The lower halves are then multiplied together on one apparatus having the capability to operate on numbers having that width, and the upper halves are combined using an apparatus having the capability to operate on the smaller width. For example, when 32-bit binary numbers are being combined, the upper and lower halves are each 16-bits. The lower halves are sign extended to 32 bits, and multiplied and added together using 32-bit hardware at the same time that the upper halves are being combined using 16-bit hardware. The upper and lower halves are then recombined in an adder.
While suitable for their intended purposes, the traditional and parallel combinatory apparatus's are different, and therefore require more space to implement than would otherwise be required, if traditional and parallel operations were able to be performed using the same apparatus.
It would therefore be beneficial to provide an apparatus which can be used to perform both traditional and parallel mathematical operations.
SUMMARY OF THE INVENTION
An apparatus for multiplying a first number and a second number together is described, each of the numbers having a width of 8, 16, 32, 64 or 128-bits or more. The 32-bit embodiment of the apparatus comprises a booth recoder having two inputs and 16 outputs, the recoder determining 16 individual booth groups associated with the second number and providing one partial product per booth group on individual ones of the 16 outputs. The apparatus further comprises first, second, third and fourth 4:2 compressors each having four inputs individually coupled to consecutive ones of the booth recoder outputs, a carry output and a sum output, fifth and sixth 4:2 compressors each having four inputs, the first and third inputs of the fifth and sixth compressors being individually coupled to the sum outputs of the first, second, third and fourth compressors respectively, the second and fourth inputs of the fifth and sixth compressors being individually coupled to the carry outputs of the first, second, third and fourth compressors respectively. The apparatus further includes a seventh 4:2 compressor having four inputs, the first and third inputs of the seventh compressor being individually coupled to the sum outputs of the fifth and sixth compressors respectively, the second and fourth inputs of the seventh compressor being individually coupled to the carry outputs of the fifth and sixth compressors respectively and an adder having two inputs individually coupled to the carry and sum outputs of the seventh compressor, and an output.
REFERENCES:
patent: 5751619 (1998-05-01), Agarwal et al.
patent: 5784305 (1998-07-01), Nadehara
patent: 5796644 (1998-08-01), Jiang
patent: 6282557 (2001-08-01), Dhong et al.
Mai Tan V.
Sun Microsystems Inc.
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