Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Patent
1998-01-28
2000-11-07
Mai, Tan V.
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
708628, G06F 752
Patent
active
061449806
ABSTRACT:
A multiplier capable of performing both signed and unsigned scalar and vector multiplication is disclosed. The multiplier is configured for use in a microprocessor and may include a partial product generator, a selection logic unit, and an adder. The multiplier is configured to receive signed or unsigned multiplier and multiplicand operands in scalar or packed vector form. The multiplier is also configured to receive a first control signal indicative of whether signed or unsigned multiplication is to be performed and a second control signal indicative of whether vector multiplication is to be performed. The multiplier is configured to calculate an effective sign for the multiplier and multiplicand operands based upon each operand's most significant bit and the control signal. The effective signs may then be used by the partial product generation unit and the selection logic to create and select a number of partial products according to Booth's algorithm. Once the partial products have been created and selected, the adder is configured to sum them and output the results, which may be signed or unsigned. When a vector multiplication is performed, the multiplier is configured to generate and select partial products so as to effectively isolate the multiplication process for each pair of vector components.
REFERENCES:
patent: 3633018 (1972-01-01), Ling
patent: 3777132 (1973-12-01), Bennett, Jr.
patent: 4163287 (1979-07-01), Munter et al.
patent: 4573136 (1986-02-01), Rossiter
patent: 4607343 (1986-08-01), Chevillat et al.
patent: 4849923 (1989-07-01), Samudrala et al.
patent: 5157624 (1992-10-01), Hesson
patent: 5206823 (1993-04-01), Hesson
patent: 5220525 (1993-06-01), Anderson et al.
patent: 5343416 (1994-08-01), Eisig et al.
patent: 5506799 (1996-04-01), Nakao
patent: 5606677 (1997-02-01), Balmer et al.
patent: 5633818 (1997-05-01), Taniguchi
patent: 5677863 (1997-10-01), Naffziger
patent: 5729481 (1998-03-01), Schwarz
patent: 5737255 (1998-04-01), Schwarz
patent: 5737257 (1998-04-01), Chen et al.
patent: 5740095 (1998-04-01), Parant
patent: 5748517 (1998-05-01), Miyoshi et al.
patent: 5841684 (1998-11-01), Dockser
patent: 5870322 (1999-02-01), Kim
A.D. Booth, "A signed binary multiplication technique," Quarterly Journal of Mechanics and Applied Mathematics, vol. 4, No. 22, pp. 236-240, 1951.
W.S. Briggs and D.W. Matula, "A 17.times.69 Bit multiply and add unit with redundant binary feedback and single cycle latency," in Proceedings of the 11.sup.th IEEE Symposium on Computer Arithmetic, Jul. 1993, pp. 163-170.
D.L. Fowler and J.E. Smith, "An accurate, high speed implementation of division by reciprocal approximation," in Proceedings of the 9.sup.th IEEE Symposium on Computer Arithmetic, Sep. 1989, pp. 60-67.
J.A. Kowaleski, et al, "A dual execution pipelined floating-point CMOS processor," in Digest of Technical Papers, IEEE International Solid-State Circuits Conference, 1996, pp. 358-359.
N.T. Quach, et al, "On fast IEEE rounding," Techincal Report No. CSL-TR-91-459, Computer Systems Laboratory, Standford University, Jan. 1991.
M.R. Santoro, et al, "Rounding algorithms for IEEE multipliers," in Proceeding of the 9.sup.th IEEE Symposium on Computer Arithmetic, Sep. 1989, pp. 176-183.
H.P. Sit, et al, "An 80 MFLOPS floating-point engine in the Intel i860 processor," in Digest of Technical Papers, IEEE International Conference on Computer Design, 1989, pp. 374-379.
Hennessy & Patterson, "Computer Architecture: A Quantitative Approach," Appendix A (pp. A-2 to A-53), Morgan Kaufmann Publishers, Inc., 1990.
Yu & Zyner, "167 MHz Radix-4 Floating Point Multiplier," SPACR Technology Business, Sun Microsystems, Inc., Sunnyvale, California, pp. 149-154, IEEE 1995.
Advanced Micro Devices , Inc.
Christen Dan R.
Kivlin B. Noel
Mai Tan V.
LandOfFree
Method and apparatus for performing multiple types of multiplica does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for performing multiple types of multiplica, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for performing multiple types of multiplica will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1651825