Method and apparatus for performing multiple simultaneous error

Details Method and apparatus for performing multiple simultaneous error Method and apparatus for performing multiple simultaneous error

1993-07-23

1995-07-11

Trammell, James P.

Excavating

371 48, H03M 1300

Patent

active

054328012

ABSTRACT:
An error may be detected and corrected from among a plurality of data values retrieved from a compact disk-read only memory (CD-ROM). As a stream of data values which have been retrieved from the CD-ROM are retransmitted by an appropriate DMA device, two different error detection schemes are simultaneously applied to identical copies of the retrieved data. The retrieved data is then evaluated to determine in which format data has been stored on the CD-ROM. A condition value which has been generated by the algorithm corresponding to the determined format of data on the CD-ROM is then evaluated to determine the probability of an error condition in the retrieved data. The two error detection schemes may differ solely in the location of the data values which are evaluated for errors.

REFERENCES:
patent: 3439331 (1969-04-01), Brown et al.
patent: 3452328 (1969-06-01), Hsiao et al.
patent: 3622985 (1971-11-01), Ayling et al.
patent: 3851306 (1974-11-01), Patel
patent: 4052698 (1977-10-01), Ragle
patent: 4348761 (1982-09-01), Berger
patent: 4379286 (1983-04-01), Yokota et al.
patent: 4454600 (1984-06-01), LeGresley
patent: 4593393 (1986-06-01), Mead et al.
patent: 4649541 (1987-03-01), Lahmeyer
patent: 4740938 (1988-06-01), Bierhoff et al.
patent: 4791641 (1988-12-01), Hillis
patent: 4882731 (1989-11-01), van Gils
patent: 4914523 (1990-04-01), Maruta
patent: 4937828 (1990-06-01), Shih et al.
patent: 4998252 (1991-03-01), Suzuki et al.
patent: 5027357 (1991-06-01), Yu et al.
patent: 5051999 (1991-09-01), Erhart et al.
patent: 5172381 (1992-12-01), Karp et al.
patent: 5206851 (1993-04-01), Cho
patent: 5289471 (1994-02-01), Tanaka et al.
P. A. Beaven, "Parallel Programmable Array-Structured CRC Generator", IBM Technical Disclosure Bulletin, vol. 21, No. 5, pp. 2058-2059 (Oct. 1978).
P. E. Boudreau et al., "Parallel CRC Generation For Multilength Characters", IBM Technical Disclosure Bulletin, vol. 15, No. 4, pp. 1314-1315 (Sep. 1972).
"8-Bit Parallel CRC Generator/Checker Using Field Programmable Logic", Design Ideas date unknown.

Affiliated with

Also associated with

Rating

Method and apparatus for performing multiple simultaneous error does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for performing multiple simultaneous error , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for performing multiple simultaneous error will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-509134