Method and apparatus for performing modular division using...

Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed

Reexamination Certificate

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C708S491000

Reexamination Certificate

active

06917957

ABSTRACT:
One embodiment of the present invention provides a system that performs modular division. This system contains a number of registers, including: a register A that is initialized with a value X; a register U that is initialized with a value Y; a register B that is initialized with a value M; and a register V that is initialized with a value 0. The system also includes a counter CA that indicates an upper bound for the most-significant non-zero bit of register A. It also includes a counter CB that indicates an upper bound for the most-significant non-zero bit of register B. The system additionally includes a temporary register H, and a temporary register L. An updating mechanism is configured to iteratively reduce the contents of registers A and B to a value of one by applying a plurality of operations to registers A, B, U and V. During operation, this updating mechanism temporarily stores A+B in the temporary register H, and temporarily stores U+V in the temporary register L. Moreover, the updating mechanism is configured to use counters CA and CB to estimate the relative magnitudes of the values stored in registers A and B instead of performing an expensive comparison operation between register A and register B.

REFERENCES:
patent: 4597568 (1986-07-01), Drexhage
patent: 6748410 (2004-06-01), Gressel et al.
patent: 2001/0054052 (2001-12-01), Arazi
Huang et al., High-Speed easily testable Galois-Field inverter, 2000, IEEE, pp. 909-918.

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