Method and apparatus for performing memory protection operations

Details Method and apparatus for performing memory protection operations Method and apparatus for performing memory protection operations

1993-02-19

1995-10-10

Treat, William M.

Boots, shoes, and leggings

395800, 39518505, 364DIG1, G06F 1214

Patent

active

054577896

ABSTRACT:
In a multiprocessor system, memory accesses by the individual processing elements are checked by a common controller. The controller includes a table of values defining valid memory locations for a task. The controller verifies the address value used by each instruction to ensure that, it is within a valid memory area for the particular task. Additional circuitry for the controller and processing elements allows finer control, of memory accessibility. The multiprocessor system may be coupled to a host computer through a buffer. Data is serially written into the buffer by the host and is read out of the buffer in parallel by the multiprocessor system. The buffer used in this system includes apparatus which calculates an error correction code from a serial data stream and passes this code, along with the data, to the multiprocessor system. The multiprocessor system includes apparatus which processes the data in parallel to handle errors occurring during transfers as indicated by the code.

REFERENCES:
patent: 4065808 (1977-12-01), Schomberg et al.
patent: 4101960 (1978-07-01), Stokes et al.
patent: 4229790 (1980-10-01), Gilliland et al.
patent: 4481580 (1984-11-01), Martin et al.
patent: 4484262 (1984-11-01), Sullivan et al.
patent: 4523273 (1985-06-01), Adams, III et al.
patent: 4569052 (1986-02-01), Cohn et al.
patent: 4574348 (1986-03-01), Scallon
patent: 4601055 (1986-07-01), Kent
patent: 4621339 (1986-11-01), Wagner et al.
patent: 4636942 (1987-01-01), Chen et al.
patent: 4665556 (1987-05-01), Fukushima et al.
patent: 4707781 (1987-11-01), Sullivan et al.
patent: 4709327 (1987-11-01), Hillis et al.
patent: 4727474 (1988-02-01), Batcher
patent: 4773038 (1988-09-01), Hillis et al.
patent: 4823281 (1989-04-01), Evangelisti et al.
patent: 4825359 (1989-04-01), Ohkami et al.
patent: 4873630 (1989-10-01), Rusterholz et al.
patent: 4891787 (1990-01-01), Gifford
patent: 5038282 (1991-08-01), Gilbert et al.
patent: 5325324 (1994-06-01), Rentzepis et al.
S. Mazor and S. Wharton "Promote User Privacy Through Secure Memory Areas" Computer Design vol. 21, No. 10, pp. 89, 90 and 92 (Oct. 1982).
A. J. Sutton and K. G. Tan, "Processor Sharing and Partitioning of Main Storage in the MP System" IBM Technical Disclosure Bulletin vol. 22, No. 5, pp. 2009-2010 (Oct. 1979).
D. Halton, "Hardware of the System 250 for Communication Control" IEEE International Switching Symposium Record, pp. 530-536 (Jun. 6, 1972).
Li et al., Polymorphic-Torus Network, 1987.
Kenneth E. Batcher, Massively Parallel Processor, MIT Press 1985, pp. 191-204.
B. Lindskog--Per-Erik Danielsson, PICAP3, A Parallel Processor Tuned For 3DIMAGE.

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