Method and apparatus for performing lane arithmetic to perform n

Details Method and apparatus for performing lane arithmetic to perform n Method and apparatus for performing lane arithmetic to perform n

1997-07-29

2000-04-04

Follensbee, John A.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

714758, G06F 1108

Patent

active

060473045

ABSTRACT:
A method and apparatus for processing network packets is disclosed. A Single Instruction Multiple Data (SIMD) architecture processor is disclosed. The SIMD processor includes several instructions designed specifically for the task of network packet processing. For example, SIMD add instructions for performing one's complement additions are included to quickly calculate Internet checksums. Furthermore, the SIMD processor includes several instructions for performing lane arithmetic.

REFERENCES:
patent: 5875123 (1999-02-01), Dao Trong et al.
Memo, T. Mallory and A. Kullberg, "Incremental Updating of the Internet Checksum", BBN Communications, Network Working Group, Request for Comments: 1141, Obsoletes: RC 1071, Jan. 1990, 2 pages.
Memo, J. Touch and B. Parham, "Implementing the Internet Checksum in Hardware", ISI, Network Working Group, Request for Comments: 1936, Category: Informational, Apr. 1996, pp. 1-21.
Memo, R. Braden, D. Borman, and C. Partridge, "Computing the Internet Checksum", ISI, Cray Research and BBN Laboratories, Network Working Group, Request for Comments: 1071, Sep. 1988, pp. 1-24.

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