Method and apparatus for performing joint timing recovery of...

Details Method and apparatus for performing joint timing recovery of... Method and apparatus for performing joint timing recovery of...

2005-09-20

2005-09-20

Liu, Shuwang (Department: 2634)

Pulse or digital communications

Receivers

Angle modulation

C375S344000, C375S376000, C327S150000, C327S159000, C710S063000

Reexamination Certificate

active

06947498

ABSTRACT:
Method and apparatus for performing joint timing recovery in a digital receiver using multiple input signals. The apparatus comprises a plurality of phase detectors, a summer, a level shifter, a loop filter and a numerically controlled oscillator NCO. The phase detectors produce a phase signal by comparing a timing signal produced by the NCO with the input signals. The phase signals are then summed and the level shifter adjusts the summed value to compensate for the number of signals used to form the sum, i.e., the summed value is adjusted to be within the input range of the NCO.

REFERENCES:
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patent: 6307413 (2001-10-01), Dalmia et al.
patent: 2002/0049936 (2002-04-01), Gutnik et al.
patent: 2002/0136342 (2002-09-01), Lee et al.
patent: 2003/0016087 (2003-01-01), Yamane et al.
patent: 2003/0085739 (2003-05-01), Totsuke
U.S. Appl. No. 60/221,709, filed on Jul. 31, 2000.
Gutnik et al.; Clock Distribution Circuits and Methods of Operating Same That Use Multiple Clock Circuits Connected By Phase Detector Circuits To Generate and Synchronize Local Clock Signals.
Lee et al.; Sample and Hold Type Fractional-N Frequency Synthesezer.
Yamane et al.; Phase-Locked Loop Circuit and Data Reproduction Apparatus.
Totsuke; Method of and Apparatus for Detecting Difference Between Frequencies, And Phase Locked Loop Circuit.

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