Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Logic design processing
Reexamination Certificate
2008-08-08
2011-12-13
Rossoshek, Helen (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Logic design processing
C716S102000, C716S103000, C716S105000, C716S106000, C716S107000, C716S108000, C716S117000, C703S013000, C703S014000
Reexamination Certificate
active
08079000
ABSTRACT:
An equivalency testing system, for formally comparing an RTLM and HLM, is presented. RTLM and HLM are first converted into DFGs RTLMDFGand HLMDFG. RTLMDFGand HLMDFGare then put into timestep form and are called RTLMtsand HLMts. A test bench CStsis selected that couples RTLMtsand HLMts. The combination of RTLMts[t], HLMts[t] and CSts[t] can have parts designated as datapath. Parts designated as datapath can be subject to a form of equivalence checking that seeks to prove equivalence by a form of inductive theorem proving that propagates symbolic values indicative of whether a node carries the same data content as another node. The theorem proving starts from initial conditions for HLMts[t] determined by partial execution of the HLM. Propagation to a combinational function output can be determined from equivalence relationships between it and another combinational function. Propagation through a multiplexer can produce a conditional symbolic value.
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Koelbl Alfred
Pixley Carl Preston
Park Vaughan Fleming & Dowler LLP
Rossoshek Helen
Sahasrabuddhe Laxman
Synopsys Inc.
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