Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
2005-03-22
2005-03-22
Tsai, Carol S (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
C702S057000, C702S064000, C702S066000, C702S069000, C702S078000, C702S079000
Reexamination Certificate
active
06871152
ABSTRACT:
An eye diagram analyzer equips each SUT data and clock signal input channel with individually variable delays in their respective paths. For a range of signal delay of n-many SUT clock cycles, the SUT clock signal delay might be set at about n/2. For each data channel there is specified a point in time relative to an instance of the delayed clock signal (data signal delay) and a voltage threshold. The specified combination (data signal delay, threshold and which channel) is a location on an eye diagram, although the trace may or may not ever go through that location. A counter counts the number of SUT clock cycles used as instances of the reference for the eye diagram, and another counter counts the number of times the specified combination of conditions was met (“hits”). After watching a specified combination for the requisite length of time or number of events, the number of SUT clock cycles involved and the associated number of hits are stored in memory using a data structure indexed by the components of the specified combination (data signal delay, threshold). Next, a new combination of data signal delay and threshold is specified and a measurement taken and recorded in the data structure. The process is repeated until all possible combinations within a stated range of data signal delay and threshold voltage (using specified resolution/step sizes for delay and voltage) have been investigated. As this process proceeds under the control of firmware within the logic analyzer, other firmware can be examining the data structure and generating a partial eye diagram visible on a display, and that will be complete soon after the measurement itself is finished.” has been changed to “An eye diagram analyzer equips each SUT data and clock signal input channel with individually variable delays in their respective paths. For a range of signal delay of n-many SUT clock cycles, the SUT clock signal delay might be set at about n/2. For each data channel there is specified a point in time relative to an instance of the delayed clock signal (data signal delay) and a voltage threshold. The specified combination (data signal delay, threshold and which channel) is a location on an eye diagram, although the trace may or may not ever go through that location.
REFERENCES:
patent: 4445192 (1984-04-01), Haag et al.
patent: 5162723 (1992-11-01), Marzalek et al.
patent: 5210712 (1993-05-01), Saito
patent: 5247544 (1993-09-01), LaRosa et al.
patent: 5400370 (1995-03-01), Guo
patent: 5978415 (1999-11-01), Kobayashi et al.
patent: 6256342 (2001-07-01), Schlag et al.
patent: 6377642 (2002-04-01), Dollard
Agilent Technologie,s Inc.
Miller Edward L.
Tsai Carol S
LandOfFree
Method and apparatus for performing eye diagram measurements does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for performing eye diagram measurements, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for performing eye diagram measurements will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3438318