Telecommunications – Receiver or analog modulated signal frequency converter – Noise or interference elimination
Reexamination Certificate
2000-11-14
2004-02-24
Nguyen, Duc M. (Department: 2685)
Telecommunications
Receiver or analog modulated signal frequency converter
Noise or interference elimination
C455S306000, C455S311000, C375S319000
Reexamination Certificate
active
06697611
ABSTRACT:
FIELD OF THE INVENTION
The invention relates generally to amplifier circuits and, more particularly, to amplifier circuits for use within receiver systems.
BACKGROUND OF THE INVENTION
A common problem in radio frequency (RF) receivers is the presence of a direct current (DC) offset in the baseband signal that is generated after down conversion. This DC offset can compromise receiver performance by, among other things, overloading the baseband amplifiers in the receiver. The DC offset is particularly large in direct conversion receivers that convert an RF receive signal directly to baseband without an intervening intermediate frequency (IF) stage. In a direct conversion receiver, the local oscillator (LO) frequency is the same as or very close to the center frequency of the RF receive signal. In addition, the LO signal is typically much larger in magnitude than the RF signal. Some of this LO signal will normally leak into the RF port of the receive mixer and combine with the RF signal before down conversion occurs. This generally results in a large DC offset in the resulting baseband signal because the LO signal mixes with itself.
In the past, a number of different techniques have been used to reduce DC offset in the baseband signal. In one approach, the baseband signal was passed through a very large, series connected capacitor before being amplified. In this approach, the capacitor and the input impedance of the following amplification stage act as a high pass filter that is supposed to pass everything except DC. Such high pass filter designs, however, are typically plagued by parasitic capacitances that make the filters difficult to implement using very large scale integration (VLSI) techniques. For example, the input impedance required for the following stage will typically be unrealizable due to parasitic shunting capacitances associated with the input of the stage and/or the large, series capacitance.
In another approach, techniques have been developed that generate an imbalance in an otherwise balanced differential line to simulate a large series capacitance to block the DC component. These techniques have been relatively successful in blocking the DC offset, but the resulting imbalance has led to other problems in the receiver circuitry. For example, one of the reasons that a balanced, differential topology is used in circuits is because of the enhanced noise rejection (e.g., rejection of noise from the power supply leads) and even order harmonic distortion cancellation characteristics associated with the topology. By purposely creating an imbalance, part of this noise rejection and distortion cancellation capability is lost. In addition, other desirable qualities of balanced circuits may also be compromised using this approach.
REFERENCES:
patent: 4644301 (1987-02-01), Hecht
patent: 5724653 (1998-03-01), Baker et al.
patent: 6075409 (2000-06-01), Khlat
patent: 6516185 (2003-02-01), MacNally
patent: 6516187 (2003-02-01), William et al.
patent: 1102413 (2001-05-01), None
Intel Corporation
Nguyen Duc M.
Schwegman Lundberg Woessner & Kluth P.A.
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