Method and apparatus for performing cyclic redundancy check sync

Details Method and apparatus for performing cyclic redundancy check sync Method and apparatus for performing cyclic redundancy check sync

1995-08-18

1998-11-03

Vo, Don N.

Pulse or digital communications

Systems using alternating or pulsating current

Plural channels for transmission of a single pulse train

375341, 375354, 371 377, 371 42, H04L 512, H04L 2302

Patent

active

058320318

ABSTRACT:
A method and apparatus for synchronizing and error checking received bitstreams of encoded information is provided. The apparatus includes a single polynomial division shift register. The method involves calculating successive syndromes using the single polynomial division shift register by shifting the received bits of information, generating a syndrome, and comparing the syndrome to a known marker syndrome.

REFERENCES:
patent: 4306305 (1981-12-01), Doi et al.
patent: 4541095 (1985-09-01), Vries
patent: 5084891 (1992-01-01), Ariyavisitakul et al.
Lin et al, "ERROR CONTROL CODING: Fundamentals and Application", Prentice Hall, pp. 85-121, 1983.

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