Method and apparatus for performing cache snoop testing using DM

Details Method and apparatus for performing cache snoop testing using DM Method and apparatus for performing cache snoop testing using DM

1994-06-09

1996-06-04

Nguyen, Hoa T.

G06F 1100, G06F 1130

Patent

active

055242081

ABSTRACT:
A method and apparatus for performing cache snoop testing on personal computers using software to initiate DMA cycles. The computer system includes an extended capabilities parallel port (ECP), which includes a 16 bit first-in first-out buffer (FIFO) that can be accessed in a test mode where software can manually write and read the FIFO. This FIFO in the ECP parallel port is used according to the present invention to implement cache snoop testing diagnostics on personal computers. In the preferred embodiment, various hardware subsystems such as system memory, the ECP port, and the DMA controller are tested first to ensure that, if a failure occurs during cache testing, the system can differentiate between cache snoop failures and other subsystem failures. Cache snoop testing according to the present invention uses the capability provided by the ECP parallel port to generate DMA cycles which transfer data from the ECP FIFO buffer into the system memory via software. Various algorithms can be used to perform cache snoop testing depending upon the cache architecture, i.e., write-through versus write-back and whether the cache system includes only first or both first and second level cache systems. Therefore, cache snoop testing can be performed reliably in software without the need for expensive custom test hardware.

REFERENCES:
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patent: 5159671 (1992-10-01), Iwami
patent: 5182752 (1993-01-01), DeRoo et al.
patent: 5185879 (1993-02-01), Yamada et al.
patent: 5228134 (1993-07-01), MacWilliams et al.

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