Method and apparatus for performing automatic test pattern gener

Details Method and apparatus for performing automatic test pattern gener Method and apparatus for performing automatic test pattern gener

1990-07-11

1994-06-07

Beausoliel,, Jr.

Excavating

371 223, 371 151, G06F 1100

Patent

active

053196473

ABSTRACT:
An apparatus for and method of performing automatic test pattern generation for a digital circuit specified registers when the process of automatic test pattern generation for one or more faults is aborted which allow detection of circuit faults by scanning the specified registers. The scan request count of the specified registers is updated, and registers having a scan request count greater than the scan request count limit are recognized as critical registers. Automatic test pattern generation is performed while regarding the critical registers as scan registers.

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patent: 4754215 (1988-06-01), Kawai
patent: 4947395 (1990-08-01), Bullinger et al.
patent: 5043986 (1991-08-01), Agrawal et al.
Cheng, Kwang-Ting and Agrawal, Vishwani D., "An Economical Scan Design for Sequential Logic Test Generation", The 19th Int'l Symposium on Fault-Tolerant Computing, Chicago, USA, Jun. 20-23, 1989, pp. 28-35.
Gupta, Rajesh, Gupta, Rajiv and Breuer, Melvin A., "Ballast: A Methodology For Partial Scan Design", The 19th Int'l Symposium on Fault-Tolerant Computing, Chicago, USA, Jun. 20-23, 1989, pp. 118-125.
V. D. Agrawal et a., A Complete Solution To The Partial Scan Problem, International Test Conference, 44 (1987), pp. 44-51.

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