Method and apparatus for performing atomic accesses in a data pr

Boots – shoes – and leggings

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395726, 3642405, 364DIG1, G06F 1314

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active

057271720

ABSTRACT:
A method and apparatus for performing atomic accesses in a data processing system (10). In one embodiment, a small number of control signals (e.g. 100-102; or 103-104; or 105-108 from FIG. 3 ) are used to provide information regarding the status of reservations between bus masters (e.g. 80), bus interfaces (e.g. 84, 86, and 92), and snoop logic (e.g. 82,88, and 90). Snoop logic (e.g. 40 in FIG. 2) is required if multiple bus masters (12 and 46) are used. The control signals allow atomic accesses to be performed in a multi-master data processing system (10), while minimizing the circuitry required to be built on-board each bus master integrated circuit processor (e.g. 152 in FIG. 3). The result is lower cost processors (152) which can operate in multi-processor systems, but which are optimized for use in single-processor systems.

REFERENCES:
patent: 5453737 (1995-09-01), Opoczynski
patent: 5506971 (1996-04-01), Gullette et al.
patent: 5548780 (1996-08-01), Krien
Motorola, Inc.; "PowerPC.TM. 603 RISC Microprocessor User's Manual;" 1994; pp. 5-1 through 5-29, 4-70 through 4-73, 10-1 through 10-56, 11-108, and 11-180.
Motorola 1994, "PowerPC 603 RISC Microprocessor User's Manual", Chapter 4.10 Memory Synchronization Instructions, pp. 4-70 -4-73.
Motorola 1994, "PowerPC 603 RISC Microprocessor User's Manual",Chapter 10.9 Processor State Signals, pp. 10-53.
Motorola 1994, "MC88110 Second Generation RISC Microprocessor User's Manual", Chapter xmem Exchange Register With Memory, pp. 10-90 -10-91.
Motorola 1994,"MC88110 Second Generation RISC Microprocessor User's Manual", Chapter 11.3.3.1 Bus Snooping Flow For Transaction Without Intent-To-Modify, pp. 11-23 -11-24.
Motorola 1994,"MC88110 Second Generation RISC Microprocessor User's Manual", Chapter 11.5.3.6 xmem Transaction, pp. 11-53 -11-56.

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