Method and apparatus for performing and operation multiple times

Details Method and apparatus for performing and operation multiple times Method and apparatus for performing and operation multiple times

1996-03-15

1998-06-02

Pan, Daniel H.

39580017, 395385, G06F 940, G06F 944

Patent

active

057615241

ABSTRACT:
A method for operating a Reduced Instruction Set Computer (RISC) processor that executes normal RISC instructions and special RISC instructions. The method comprises the step of controlling the RISC processor to perform a single operation, using a single functional unit of the RISC processor, in response to each normal RISC instruction. The method also comprises the step of controlling the RISC processor to perform multiple operations, using multiple functional units of the RISC processor in parallel, in response to each special RISC instruction.

REFERENCES:
patent: 5278975 (1994-01-01), Ishihata et al.
patent: 5440747 (1995-08-01), Kiuchi
patent: 5481683 (1996-01-01), Karim
patent: 5517603 (1996-05-01), Kelley et al.

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