Method and apparatus for performing a vector reduction

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G06F 15347

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048398454

ABSTRACT:
A vector data reduction to a scalar result in which adjacent elements in the vector are paired and each pair is sequentially reduced in an arithmetic unit organized for so-called pipe line operation is described. The results of each paired pass are stored as result vector elements and these elements are similarly paired, sequentially operated upon, and stored as result vector elements. The process continues until there is but one pair left which is operated upon to produce a singular, scalar result.

REFERENCES:
patent: 3761698 (1973-04-01), Stephenson
patent: 3900723 (1975-08-01), Bethany et al.
patent: 4435765 (1984-03-01), Vehida et al.
patent: 4507728 (1985-03-01), Sakamoto et al.
patent: 4525796 (1985-06-01), Omoda et al.
Oberman, Digital Circuits For Binary Arithmetic, John Wiley & Sons, 1979, pp. 107-108.

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