Electrical computers and digital processing systems: processing – Architecture based instruction processing
Patent
1998-01-23
2000-08-29
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Architecture based instruction processing
712220, 712223, 712224, G06F 930
Patent
active
061122912
ABSTRACT:
A microprocessor 1 has an instruction fetch/decode unit 10a-c, a plurality of execution units, including an arithmetic and load/store unit D1, a multiplier M1, an ALU/shifter unit S1, an arithmetic logic unit ("ALU") L1, a shared multiport register file 20a from which data are read and to which data are written, and a memory 22. The microprocessor can execute an instruction which shifts a source operand a specified number of bits and saturates the result if a numerical overflow would result from the shift. Execution unit S1 has circuitry for saturating a destination operand by setting all bits within the destination to represent a most positive or a most negative number in a same single instruction execution phase in which the shift would have occurred if not for the overflow. The saturation circuitry examines the source operand prior to shifting to determine if the destination should be saturated.
REFERENCES:
patent: 5572689 (1996-11-01), Gallup et al.
patent: 5663808 (1997-09-01), Park
patent: 5781789 (1998-07-01), Narayan
Leach Jerald G.
Scales Richard H.
An Meng-Ai T.
Brady III W. James
Laws Gerald E.
Monestime Mackly
Telecky Jr. Frederick J.
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