Method and apparatus for pattern sensitivity stress testing of m

Details Method and apparatus for pattern sensitivity stress testing of m Method and apparatus for pattern sensitivity stress testing of m

1994-12-05

1998-07-07

Gregory, Bernarr E.

Excavating

371 211, 371 212, 371 151, H01L 310328, G11C 2900

Patent

active

H00017418

ABSTRACT:
A method and apparatus for stress testing a computer memory system is disclosed. A sequential series of bit patterns, comprising 1's and 0's, is impressedd upon a computer memory so that, during testing, every memory cell stores a 1 while the eight adjacent neighboring memory cell stores 0's. Subsequently, the complimentary bit patterns are impressed upon memory, wherein every memory cell, at some time during the test, stores a 0 while the eight immediately adjacent neighboring memory cells store 1's. The disclosed bit pattern maximizes stress on the cells, In an interleaved dual memory bank configuration, memory cells are sequentially accessed from the highest to the lowest address of one memory bank, while memory cells are sequentially accessed from the lowest to the highest memory address in the other memory bank. Toggling successive memory accesses between the dual interleaved memory banks maximizes stress on the address driver components of the computer memory system. Preferably, the dual memory banks are simultaneously tested with complementary bit patterns to also maximize stress on the data bus driver and associated components and to maximize demand on the power supply system.

REFERENCES:
patent: 5375091 (1994-12-01), Berry, Jr. et al.
Article by Abadir et al., entitled "Functional Testing of Semiconductor Random Access Memories" published by Computing Surveys, vol. 15, No. 3, Sep. 1983.
Article by Knaizuk et al., entitled "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories" published by IEEE Transaction on Computing, vol. C-26, No. 11, Nov. 1977 pp. 1141-1144.

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