Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2001-04-30
2003-05-13
Hjerpe, Richard (Department: 2674)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S098000, C345S211000, C345S501000, C341S101000
Reexamination Certificate
active
06563485
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to transmitters that receive a parallel input and provide a serial output and more particularly to transmitters that provide a serial output for low voltage differential signals.
BACKGROUND OF THE INVENTION
Transmission of data from a processing engine to a display device for subsequent presentation or display is known. For example, data may be transmitted from a video graphics controller, or video graphics processing engine, to an LCD (liquid crystal diode) display panel for subsequent display. Because of the digital nature of the data (eg. binary signaling switching between 0 volts and the voltage supply), electromagnetic interference (EMI) is generated. For relatively small amounts of data transmissions, the resulting EMI is practically negligible (i.e., the EMI does not adversely affect circuit operation and is below EMI levels established by regulatory agencies such as the Federal Communications Commission (FCC)).
As the LCD display increases in size and/or the complexity of the displayed data increases, the amount of data conveyed from the video graphics circuit is similarly increased. Not surprisingly, the generated EMI increases correspondingly to the increase in data transmission. In fact, in many high volume data transmissions, the EMI generated exceeds FCC regulations. Systems, such as computers, that employ the high volume data transmissions that are not FCC compliant are, as a result, not marketable.
To combat the EMI problem created from high volume data transmissions, a standard Low Voltage Differential Signaling (LVDS) for interface circuits has been developed. In particular, TIA/EIA-644 LVDS standard governs LVDS transmissions.
The TIA/EIA-644 standard provides general specifications as to the acceptable operating criteria for low voltage differential signaling. Such specifications require that signal transmissions be done using differential signaling, which substantially reduces the affects of the EMI generated by having the differential signals transmitted over a twisted wire pair, or at least an equivalent transmission medium. The specifications also dictate the signaling levels, such as the signal magnitude and the DC offset voltage. While the TIA/EIA-644 provides operational parameters, it does not provide information as to specific circuit implementations.
One TIA/EIA-644 standard compliant circuit uses two pairs of cascaded transistors, which are switched as a full bridge inverter. The interconnecting nodes of each pair of cascaded transistors provides the differential output, while the ends of each of the pair of cascaded transistors are coupled to a current source and circuit return, respectively. The DC offset as specified in the standard is achieved by controlling the conductive impedances of the transistors to provide a voltage divider circuit. While this circuit works well in many applications, controlling the conductive impedances may provide manufacturing difficulties and, if the conductive impedances drift due to manufacturing differences or gate drive circuits, the resulting differential output may not have the specified DC offset.
This problem in the prior art is overcome by a method and apparatus, as disclosed in U.S. Pat. Nos. 5,959,601 and 6,118,438, for providing serial transmission of a parallel input. This is accomplished by a parallel input serial output transmitter that includes a shift register operably coupled to receive a parallel input and to provide data serially to a gating circuit. The gating circuit, based on the state of the data it receives, generates a drive signal which causes a switching circuit to route current from a first current source to a second current source over different paths to produce a serial output. A bias circuit is coupled to the switching circuit to bias the serial output to a desired level.
However, as the geometry of integrated circuits becomes smaller, the magnitude of the supply voltage is necessarily reduced. However, as explained in the prior art references, the 1.2 volt level for the DC offset is an industry standard.
Therefore a need exists for a method and apparatus that is TIA/EIA-644 compliant and that also operates at lower source voltage levels.
REFERENCES:
patent: 5959601 (1999-09-01), Ho et al.
patent: 6107946 (2000-08-01), Jeong
patent: 6118438 (2000-09-01), Ho
patent: 6147672 (2000-11-01), Shimamoto
patent: 6480180 (2002-11-01), Moon
Chan Nancy Ngar Sze
Chow Hugh Hin-Poon
Ho Edward Chak Cheung
ATI Technologies Inc.
Hjerpe Richard
Nguyen Francis
Vedder Price Kaufman & Kammholz
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