Method and apparatus for parallel high speed data transfer

Details Method and apparatus for parallel high speed data transfer Method and apparatus for parallel high speed data transfer

1996-09-10

1999-02-16

Butler, Dennis M.

395309, G06F 104

Patent

active

058729593

ABSTRACT:
The present invention concerns a method for eliminating or reducing clock skew introduced by differing signal propagation delays across a data bus. At high bus clock frequencies the time delay differences caused by path length differences can be catastrophic and must be eliminated by expensive layout techniques. An input/output (I/O) architecture is proposed here which tailors a delay to each individual data line, and thereby aligns all the incoming data. Furthermore, a clock signal is provided to indicate the optimal data sampling time. In the described embodiment, this circuit enables the transmission of four 32 bit words in parallel in one clock cycle of a 250 MHz processor.

REFERENCES:
patent: 5513377 (1996-04-01), Capowski et al.
patent: 5572722 (1996-11-01), Vogley
patent: 5692165 (1997-11-01), Jeddeloh et al.

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