Method and apparatus for parallel and pipelining transference of

Details Method and apparatus for parallel and pipelining transference of Method and apparatus for parallel and pipelining transference of

1997-05-05

1998-12-01

An, Meng-Ai T.

Multiplex communications

Wide area network

Packet switching

39520053, 3952006, 3952008, 370466, 370463, 370359, G06F 1300

Patent

active

058450726

ABSTRACT:
A common macro interface between chips that have design features in common and communicate with each other. The common macro interface (CMI) uses VHDL (VHSIC Hardware Description Language) which is the industry standard hardware design language. A common protocol is provided to resolve communication problems and comprises four signals: request; acknowledge request; data acknowledge, and read/write. A freeway system within the interfaces facilitates parallel and pipelining processes and an arbiter (also called a scheduler) is placed in front of every slave resource to control the traffic independently and to avoid traffic collisions from locking the freeway. The freeway is unique for each integrated circuit. Accordingly, macros may be moved from chip to chip without requiring complete system modifications and the effort involved in designing macros common to several chips may be shared.

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