Method and apparatus for page recall of data in an nonvolatile D

Details Method and apparatus for page recall of data in an nonvolatile D Method and apparatus for page recall of data in an nonvolatile D

1990-09-20

1992-09-08

Popek, Joseph A.

Static information storage and retrieval

Addressing

Byte or page addressing

365236, G11C 800

Patent

active

051464314

ABSTRACT:
In a non-volatile DRAM (NVDRAM) memory device comprised of NVDRAM cells, each comprising a DRAM cell and an EEPROM cell, a method and apparatus for the page recall of data whereby the page recall start address may be specified by the user through the memory device's external control pins. A page of memory cells is defined as all of the memory cells connected to a single word line. During any recall operation, data are recalled from EEPROM to DRAM in only one memory cell per bit line. The externally specified page recall start address is input onto an external pad. It is then transmitted through an address selector circuit into the inputs of a counter circuit. The outputs of the counter circuit serve as the page recall start address, which reenters the address selector circuitry to be transmitted to address decoding circuitry.

REFERENCES:
patent: 4471471 (1984-09-01), DeMaria
patent: 4611309 (1986-09-01), Chuang et al.
Terada et al., "A New Architecture for the NVRAM an EEPROM Backed-up Dynamic RAM", IEEE Journal of Solid-State Circuits, vol. 23, No. 1, Feb. 1988, pp. 86-90.
Yamauchi et al., "A Versatile Stacked Storage Capacitor On Flotox Cell For Megabit NVRAM Applications", IEDM 89, Dec. 1989, pp. 25.5.1-25.5.4.

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