Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-11-26
2004-11-09
Zarneke, David A. (Department: 2829)
Semiconductor device manufacturing: process
With measuring or testing
Reexamination Certificate
active
06815232
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the field of semiconductor device manufacturing and, more particularly, to a method and apparatus for overlay control using multiple targets.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
The technologies underlying semiconductor processing tools have attracted increased attention over the last several years, resulting in substantial refinements. However, despite the advances made in this area, many of the processing tools that are currently commercially available suffer certain deficiencies. In particular, such tools often lack advanced process data monitoring capabilities, such as the ability to provide historical parametric data in a user-friendly format, as well as event logging, real-time graphical display of both current processing parameters and the processing parameters of the entire run, and remote, i.e., local site and worldwide, monitoring. These deficiencies can engender non-optimal control of critical processing parameters, such as throughput, accuracy, stability and repeatability, processing temperatures, mechanical tool parameters, and the like. This variability manifests itself as within-run disparities, run-to-run disparities and tool-to-tool disparities that can propagate into deviations in product quality and performance, whereas an ideal monitoring and diagnostics system for such tools would provide a means of monitoring this variability, as well as providing means for optimizing control of critical parameters.
Semiconductor devices are manufactured from wafers of a semiconducting material. Layers of materials are added, removed, and/or treated during fabrication to create the electrical circuits that make up the device. The fabrication essentially comprises four basic operations. Although there are only four basic operations, they can be combined in hundreds of different ways, depending upon the particular fabrication process.
The four operations typically used in the manufacture of semiconductor devices are:
layering, or adding thin layers of various materials to a wafer from which a semiconductor device is produced;
patterning, or removing selected portions of added layers;
doping, or placing specific amounts of dopants in the wafer surface through openings in the added layers; and
heat treatment, or heating and cooling the materials to produce desired effects in the processed wafer.
As technology advances facilitate smaller critical dimensions for semiconductor devices, the need for reduction of errors increases dramatically. Proper formation of sub-sections within a semiconductor device is an important factor in ensuring proper performance of the manufactured semiconductor device. Critical dimensions of the sub-sections generally have to be within a predetermined acceptable margin of error for semiconductor devices to be within acceptable manufacturing quality.
One important aspect of semiconductor manufacturing is overlay control. Overlay control involves measuring the misalignment between two successive patterned layers on the surface of a semiconductor device. Generally, minimization of misalignment errors is important to ensure that the multiple layers of the semiconductor devices are connected and functional. As advances in technology facilitate smaller critical dimensions for semiconductor devices the need for the reduction of misalignment errors increases significantly.
Generally, a set of photolithography steps is performed on a lot of wafers using a semiconductor manufacturing tool commonly referred to as an exposure tool or a stepper. The manufacturing tool communicates with a manufacturing framework or a network of processing modules. The manufacturing tool is generally connected to an equipment interface. The equipment interface is connected to a machine interface to which the stepper is connected, thereby facilitating communications between the stepper and the manufacturing framework. The machine interface may generally be part of an advanced process control (APC) system. The APC system initiates a control script, which can be a software program that automatically retrieves the data needed to execute a manufacturing process. The input parameters that control the manufacturing process are revised periodically in a manual fashion. As the need for higher precision manufacturing processes are required, improved methods are needed to revise input parameters that control manufacturing processes in a more automated and timely manner.
Typical overlay control techniques employ a feedback control methodology, where after patterning a layer of photoresist material, metrology data is collected to measure misregistration, or overlay error, between the photoresist layer and underlying layer(s). The feedback generated from the overlay error measurement may be provided to a process controller for updating the control signals of the photolithography tools for subsequently processed wafers. The overlay error may also be used in a fault detection scheme, whereby wafers with overlay errors that exceed a predetermined threshold are reworked by removing the errant photoresist layer and patterning a new one.
Referring to
FIGS. 1A and B
, top and cross-section views of a semiconductor device
100
are provided, respectively. A first overlay target
110
is formed on a first process layer
120
. A second process layer
130
, typically a photoresist layer, is formed over the first process layer
120
. When the photoresist material in the second process layer
130
is patterned, a second overlay target
140
is defined in the pattern. Using the first and second overlay targets
110
,
140
, the misregistration between the pattern in the second process layer
130
and the first process layer
120
is measured in the X and Y directions. If the misregistration is sufficiently large, the second process layer
130
may be removed and reworked. The measured misregistration may also be used to control the photolithography stepper to reduce the amount of overlay error for subsequent exposure processes. The overlay targets
110
,
140
shown in
FIGS. 1A and 1B
are commonly referred to as box-in-box overlay targets, although other types of target geometries may be used.
Overlay error may be measured in the X and Y directions by measuring the distances between the sides of the targets
110
,
140
. For example, to measure overlay error in the X direction, the distance between sides
111
,
141
may be compared to the distance been sides
112
,
142
. The overlay error is the half the difference between the measured distances. If the distance between the sides
111
,
141
is 0.05 microns and the distance between the sides
112
,
142
is 0.03 microns, the overlay error in the X direction is (0.05−0.03)/2=+0.01 micron. A distance of 0.04 microns for each group of sides would represent an overlay error of zero. A similar process may be used for determining overlay error in the Y direction.
Typically, each patterned layer is aligned by measuring X and Y overlay error with respect to a single set of overlay targets. The alignment process is typically performed iteratively as additional process layers are added to the device
100
. However, because a particular wafer may be processed by different photolithography tools throughout the fabrication cy
Bode Christopher A
Edwards Richard D
Jones Gary K
Geyer Scott B.
Williams, Morgan & Amersen
Zarneke David A.
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