Boots – shoes – and leggings
Patent
1993-03-24
1995-12-26
Chan, Eddie P.
Boots, shoes, and leggings
395445, 395483, 395471, 3642434, 36424341, 3642663, 3642715, 364DIG1, 371 511, 371 62, G06F 1200, G06F 1300
Patent
active
054796415
ABSTRACT:
A cache circuit for a computer microprocessor and a method for performing cache operations (e.g., read and write) in a single, short cycle using overlapped clocking. The cache includes a tag array, a status array, and a data array. Parity information is generated and checked to verify data and tag integrity. The parity field is stored in a status array physically separate from the tag array. The status array is offset in timing so that it lags behind the tag array for both read and write operations. Therefore, fields in the status array can be written in the early part of the next clock cycle without affecting the tag array or another operation that may be scheduled for the next time cycle.
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Chu Ching-Hua
Nadir James
Asta Frank J.
Chan Eddie P.
Intel Corporation
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