Method and apparatus for output deselecting of data during test

Details Method and apparatus for output deselecting of data during test Method and apparatus for output deselecting of data during test

1995-08-10

1996-07-23

Canney, Vincent P.

Excavating

39518306, G06F 1100

Patent

active

055397530

ABSTRACT:
A circuit, as a logic circuit or a memory circuit, having testing latches. The testing latches include an input latch, a slave latch, and true and complement output latches. The output of the slave latch is NANDed with a DESELECT signal to deselect the output latches. The testing latches can be used in a method of characterizing or testing a memory or logic integrated circuit with scannable output latches. At least one output latch has an input latch, a slave latch, and an output latch which may contain a Complement Latch, and a True latch. In the testing process an output of the slave latch is NANDed with a deselect signal to allow testing or characterization by masking known "fail" signals.

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