Method and apparatus for ordering and queueing multiple memory r

Details Method and apparatus for ordering and queueing multiple memory r Method and apparatus for ordering and queueing multiple memory r

1989-02-03

1993-06-22

Gossage, Glenn

Boots, shoes, and leggings

364DIG1, 3642318, 36424291, 36496426, 395400, G06F 1316, G06F 1200

Patent

active

052222233

ABSTRACT:
In a pipelined computer system 10, memory access functions (requests) are simultaneously generated from a plurality of different locations. These multiple requests are passed through a multiplexer 50 according to a prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. In this manner, the complex task of converting virtual-to-physical addresses is accomplished for all memory access requests by a single translation buffer 30. The physical address output from the translation buffer 30 are passed to a cache 28 through a second multiplexer 40 according to a second prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. The first and second prioritization schemes differ, in that the memory is capable of handling other requests while a higher priority "miss" is pending. Thus, the prioritization scheme temporarily suspends the higher priority request while the desired data is being retrieved from main memory 14, but continues to operate on a lower priority request so that the overall operation will be enhanced if the lower priority request hits in the cache 28.

REFERENCES:
patent: 3949379 (1976-04-01), Ball
patent: 4392200 (1983-07-01), Arulpragasam
patent: 4500958 (1985-02-01), Manton et al.
patent: 4551799 (1985-11-01), Ryan et al.
patent: 4695943 (1987-09-01), Keeley et al.
patent: 4722046 (1988-01-01), Kasrazadeh et al.
patent: 4729093 (1988-03-01), Mothersole et al.
patent: 4872111 (1989-10-01), Daberkow et al.
patent: 4875160 (1989-10-01), Brown, III
patent: 5006980 (1991-04-01), Sanders et al.
patent: 5027270 (1991-06-01), Riordan et al.
Fossum et al., "An Overview of the VAX 8600 System," Digital Technical Journal, No. 1, Aug. 1985, pp. 8-23.
Troiani et al., "The VAX 8600 I Box, A Pipelined Implementation of the VAX Architecture," Digital Technical Journal, No. 1, Aug. 1985, pp. 24-42.
Levy and Eckhouse, Jr., Computer Programming and Architecture, The VAX-11, Digital Equipment Corporation, 1980, pp. 263-276, 296-303, 351-368.
G. Desrochers, Principles of Parallel and Multiprocessing, Intertext Publications, Inc., McGraw-Hill Book Co., 1987, pp. 68-71.
A. J. Smith, "Pipelining," Computing Surveys, vol. 14, No. 3 (Sep. 1982), p. 518.
Fossum et al., "New VAX Squeezes Mainframe Power into Mini Package," Computer Design, vol. 24, No. 3, (Mar. 1985), Littleton, Mass., pp. 173-181.

Affiliated with

Also associated with

Rating

Method and apparatus for ordering and queueing multiple memory r does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for ordering and queueing multiple memory r, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for ordering and queueing multiple memory r will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1446451