Method and apparatus for optimizing supervisor mode store operat

Details Method and apparatus for optimizing supervisor mode store operat Method and apparatus for optimizing supervisor mode store operat

1993-10-07

1997-02-25

Chan, Eddie P.

395445, G06F 1208

Patent

active

056066872

ABSTRACT:
A system and method for performing conditionally cache allocate operations to a data cache in a computer system. As supervisor mode operations typically do not experience data locality of accesses frequently found in user mode operations, it has been determined that performance benefits can be achieved by inhibiting cache allocate operations during supervisor mode. When a write miss to the cache occurs, the memory management unit checks the state of the processor status register to determine the mode of the processor. If the processor status register indicates that the processor is in supervisor mode, the memory management unit issues a signal to the data cache controller that the data is non-cacheable. When the data cache controller receives a non-cacheable signal, the cache allocate process is not performed. The non-cacheable signal is issued by the memory management unit while the processor is in supervisor mode regardless of the state of the cacheable status bit associated with the memory. Thus, if the processor is not in supervisor mode, the memory management unit will issue a non-cacheable signal to-the data cache controller based upon the state of the cacheable status bit associated with the memory. This status bit is typically found in the corresponding page table entry in the page table of a translation look aside buffer. Therefore, although a supervisor mode operation inhibits a cache allocate operation, subsequent non-supervisor mode operations to the same data will proceed based upon the state of the cacheable status bit associated with the memory.

REFERENCES:
patent: 5091846 (1992-02-01), Sachs et al.
patent: 5371872 (1994-12-01), Larsen et al.
patent: 5491799 (1996-02-01), Kreuzenztein et al.

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