Method and apparatus for optimizing high speed performance and h

Details Method and apparatus for optimizing high speed performance and h Method and apparatus for optimizing high speed performance and h

1993-02-26

1995-06-20

Wieder, Kenneth A.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

324768, 437 8, H01L 2100

Patent

active

054263751

ABSTRACT:
MOS integrated circuit fabrication processes may be optimized for yield rather than for hot carrier lifetime by compensating for oversize MOS channel lengths with increased V.sub.cc power supply voltage, and by compensating for undersized MOS device channel lengths with decreased V.sub.cc. Where channel lengths are greater than necessary, V.sub.cc is increased to increase switching times, while still operating the integrated circuit in a regime ensuring at least a minimum hot carrier lifetime. A test MOS device is fabricated on the integrated circuit substrate and in a test mode the test device substrate current I.sub.bb is measured. The measured I.sub.bb is then correlated with known I.sub.bb data to ascertain whether the channel length and DC hot carrier lifetime are acceptable, both for the test device and all MOS devices in the integrated circuit. The measured I.sub.bb value may be used with a look-up table to manually adjust the V.sub.cc power supply to the integrated circuit to compensate for channel length variation. The measured I.sub.bb value may be translated into a desired compensating value of V.sub.cc, and the integrated circuit so labelled, electrically or by package marking. Alternatively, the measured I.sub.bb value may control on an-chip circuit coupled to an off-chip voltage regulator to automatically adjust V.sub.cc to a level ensuring at least a minimum hot carrier lifetime for the integrated circuit.

REFERENCES:
patent: 5103166 (1990-09-01), Jeon
patent: 5286656 (1994-04-01), Keown

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