Method and apparatus for optimizing a sector cache tag, block an

Details Method and apparatus for optimizing a sector cache tag, block an Method and apparatus for optimizing a sector cache tag, block an

1993-04-20

1996-07-23

Swann, Tod R.

395445, G06F 1206

Patent

active

055398944

ABSTRACT:
A sector cache tag structure for a computer system with a cache memory and a maximum amount of system memory is disclosed. Upon initial power-up of the computer system, the amount of system memory installed in the computer system is determined. A minimum number of sub-blocks for the cache memory is selected such that when less than the maximum amount of system memory is installed, fewer sub-blocks are selected for each block in the cache memory. Based on the optimal number of sub-blocks selected for the amount of installed memory, a plurality of cache tags, block valid bits and sub-block valid bits are stored. The number of cache tags and block valid bits is equivalent to the number of blocks in the cache memory, and the number of sub-block valid bits is equal to the number of sub-blocks. The cache tags are stored in a cache tag random access memory (RAM). The block valid bits are stored in a block valid RAM which is large enough to store all the block valid bits for a minimum amount of memory installed in the computer system, and the sub-block valid bits are stored in a sub-block valid RAM comprising a total size to support the maximum amount of memory installed.

REFERENCES:
patent: 4493026 (1985-01-01), Olnowich
patent: 5014195 (1991-05-01), Farrell
patent: 5257360 (1993-10-01), Schnizlein et al.
patent: 5301296 (1994-04-01), Mohri et al.
patent: 5367653 (1994-11-01), Coyle et al.
patent: 5414828 (1995-05-01), Yarkoni
patent: 5465342 (1995-11-01), Walsh

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