Method and apparatus for optimizing a gated clock structure usin

Details Method and apparatus for optimizing a gated clock structure usin Method and apparatus for optimizing a gated clock structure usin

1996-11-19

1999-11-09

Teska, Kevin J.

Boots, shoes, and leggings

G06F 1750

Patent

active

059800925

ABSTRACT:
A method and apparatus for using an optimization tool to optimize a design that uses a gated clock structure. In short, the present invention allows a standard optimizer tool to determine the relative timing of two or more signals that arrive at a logic gate, wherein the logic gate forms a gated clock signal. Typically, standard optimizer tools can only check the relative timing between two or more signals that arrive at a storage element. In accordance with the present invention, selected logic gates may be modeled as a storage element. Thus, a standard optimizer tool may be used to correctly optimize a design that uses a gated clock structure, and in particular, to correctly optimize the logic that provides the clock and enable signals to a clock gating element.

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