Method and apparatus for optimizing a circuit design having mult

Details Method and apparatus for optimizing a circuit design having mult Method and apparatus for optimizing a circuit design having mult

1996-11-19

1999-09-21

Teska, Kevin J.

Boots, shoes, and leggings

G06F 1750

Patent

active

059562560

ABSTRACT:
A method and apparatus for optimizing a circuit design having multi-cycle paths therein. In an exemplary embodiment, a circuit design having a number of multi-cycle paths may be optimized by: identifying at least one of the number of multi-cycle paths within the circuit design, and identifying the corresponding qualified clocks associated therewith; replacing selected ones of the corresponding clocks with replacement clocks; and optimizing the circuit design using the replacement clocks. By using a replacement clock that has a clock period equal to the corresponding clock, which is typically a qualified clock, a standard optimization tool may correctly optimize the circuit design.

REFERENCES:
patent: 4758953 (1988-07-01), Morita et al.
patent: 4831543 (1989-05-01), Mastellone
patent: 4918614 (1990-04-01), Modarres et al.
patent: 5050091 (1991-09-01), Rubin
patent: 5164908 (1992-11-01), Igarashi
patent: 5175696 (1992-12-01), Hooper et al.
patent: 5191541 (1993-03-01), Landman et al.
patent: 5222029 (1993-06-01), Hooper et al.
patent: 5255363 (1993-10-01), Seyler
patent: 5267175 (1993-11-01), Hooper
patent: 5341309 (1994-08-01), Kawata
patent: 5349659 (1994-09-01), Do et al.
patent: 5355317 (1994-10-01), Talbott et al.
patent: 5357440 (1994-10-01), Talbott et al.
patent: 5359523 (1994-10-01), Talbott et al.
patent: 5359537 (1994-10-01), Saucier et al.
patent: 5361357 (1994-11-01), Kionka
patent: 5398195 (1995-03-01), Kim
patent: 5406497 (1995-04-01), Altheimer et al.
patent: 5416721 (1995-05-01), Nishiyama et al.
patent: 5418733 (1995-05-01), Kamijima
patent: 5418954 (1995-05-01), Petrus
patent: 5440720 (1995-08-01), Baisuck et al.
patent: 5448497 (1995-09-01), Ashar et al.
patent: 5452239 (1995-09-01), Dai et al.
patent: 5455931 (1995-10-01), Camporese et al.
patent: 5483461 (1996-01-01), Lee et al.
patent: 5485396 (1996-01-01), Brasen et al.
patent: 5490266 (1996-02-01), Sturges
patent: 5490268 (1996-02-01), Matsunaga
patent: 5491640 (1996-02-01), Sharma et al.
patent: 5493508 (1996-02-01), Dangelo et al.
patent: 5507029 (1996-04-01), Granato et al.
patent: 5517638 (1996-05-01), Szczepanek
patent: 5579510 (1996-11-01), Wang et al.
patent: 5600567 (1997-02-01), Kucukcakar et al.
patent: 5600824 (1997-02-01), Williams et al.
patent: 5644499 (1997-07-01), Ishii
patent: 5684808 (1997-11-01), Valind
patent: 5708801 (1998-01-01), Williams et al.
Tufte, "CML III Bipolar Standard Cell Library", Proceedings of the 1988 Bipolar Circuits and Technology Meeting, Minneapolis, Minnesota, Sep., 1988, pp. 180-182.

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