Method and apparatus for optimally tuning clock signals for digi

Details Method and apparatus for optimally tuning clock signals for digi Method and apparatus for optimally tuning clock signals for digi

1983-12-01

1985-10-08

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

364900, H03K 513

Patent

active

045462690

ABSTRACT:
In a first searching mode of the control program for the microprocessor, the microprocessor starts with a selected clock input and associated delay circuit and sets the delay circuit to an initial clocking point which is intermediate to the minimum and maximum delay points. The microprocessor then, at each pass of the control program, successively increments the delay period interposed by the delay circuit to cause the clock pulse to arrive later and later in time at the clock input until the associated circuit fails, to indicate the late clocking failure limit. In the second searching mode of the microprocessor control program, the microprocessor starts at the late clocking failure limit and at each subsequent pass of the program successively decrements the delay period interposed by the delay circuit to cause the clock signal to arrive earlier and earlier in time until the semiconductor device fails again, to indicate the early clocking failure limit. The early clocking failure limit and the late clocking failure limit together define the clocking window for the semiconductor device. The microprocessor sets the delay circuit to the mid-point of the clocking window which is the optimal clocking point for the particular clock input. The microprocessor repeats this procedure for each delay circuit and associated clock input to optimize the clocking of all of the logic circuits and thereby optimize computer performance during the normal operating mode of the computer.

REFERENCES:
patent: 3617889 (1971-11-01), Rabinowitz
patent: 4101761 (1982-07-01), Merrymun
patent: 4290022 (1981-09-01), Puckette
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patent: 4337433 (1982-06-01), Yoshimura
patent: 4338569 (1982-07-01), Petrich
patent: 4366540 (1982-12-01), Berglund et al.
patent: 4379265 (1983-04-01), Catiller
patent: 4435757 (1984-03-01), Pross
patent: 4490821 (1984-12-01), Lacher

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