Method and apparatus for operating multi-unit array of memories

Details Method and apparatus for operating multi-unit array of memories Method and apparatus for operating multi-unit array of memories

1988-02-01

1990-02-06

Fleming, Michael R.

Excavating

371 401, G06F 1110

Patent

active

048993425

ABSTRACT:
A method and apparatus are disclosed for operating a multi-unit memory system so that one of such units may readily be replaced in service. The system comprises an error correction code (ECC) generation circuit, a plurality of read/write memory units and at least one spare read/write memory unit. The ECC circuit generates an error correction code for each block of data to be stored in the system and supplies this code along with the block of data to the memory units for storage. The system further comprises means for generating from a sequence of blocks of data and associated error correction codes retrieved from these memory units a sequence of bits which correct an error in the information retrieved from one memory unit and means for writing this sequence of correction bits to the spare read/write memory unit. Advantageously, the system also comprises means for rewriting the sequence of correction bits to a memory unit after a faulty memory unit has been repaired or replaced. Preferably, the sequence of correction bits is generated by the same ECC circuit which generates the error correction codes; and the sequence of correction bits is connected to the spare memory unit, a repaired unit or a replacement unit through an array of multiplexers.

REFERENCES:
patent: 4646304 (1987-02-01), Fossati
patent: 4654847 (1987-03-01), Dutton
patent: 4703453 (1987-10-01), Shinoda
patent: 4710934 (1983-12-01), Traynor

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