Measuring and testing – With fluid pressure
Reexamination Certificate
1999-01-04
2001-08-14
Williams, Hezron (Department: 2856)
Measuring and testing
With fluid pressure
C451S289000, C451S388000
Reexamination Certificate
active
06272902
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method and an apparatus for testing a chemical mechanical polishing head and more particularly, relates to a method and an apparatus for testing a chemical mechanical polishing head that can be carried out off-line such that down time of the chemical mechanical polishing apparatus is not required.
BACKGROUND OF THE INVENTION
Apparatus for polishing thin, flat semiconductor wafers is well-known in the art. Such apparatus normally includes a polishing head which carries a membrane for engaging and forcing a semiconductor wafer against a wetted polishing surface, such as a polishing pad. Either the pad, or the polishing head is rotated and oscillates the wafer over the polishing surface. The polishing head is forced downwardly onto the polishing surface by a pressurized air system or, similar arrangement. The downward force pressing the polishing head against the polishing surface can be adjusted as desired. The polishing head is typically mounted on an elongated pivoting carrier arm, which can move the pressure head between several operative positions. In one operative position, the carrier arm positions a wafer mounted on the pressure head in contact with the polishing pad. In order to remove the wafer from contact with the polishing surface, the carrier arm is first pivoted upwardly to lift the pressure head and wafer from the polishing surface. The carrier arm is then pivoted laterally to move the pressure head and wafer carried by the pressure head to an auxiliary wafer processing station. The auxiliary processing station may include, for example, a station for cleaning the wafer and/or polishing head; a wafer unload station; or, a wafer load station.
More recently, chemical-mechanical polishing (CMP) apparatus has been employed in combination with a pneumatically actuated polishing head. CMP apparatus is used primarily for polishing the front face or device side of a semiconductor wafer during the fabrication of semiconductor devices on the wafer. A wafer is “planarized” or smoothed one or more times during a fabrication process in order for the top surface of the wafer to be as flat as possible. A wafer is polished by being placed on a carrier and pressed face down onto a polishing pad covered with a slurry of colloidal silica or alumina in de-ionized water.
A schematic of a typical CMP apparatus is shown in
FIGS. 1A and 1B
. The apparatus
10
for chemical mechanical polishing consists of a rotating wafer holder
14
that holds the wafer
10
, the appropriate slurry
24
, and a polishing pad
12
which is normally mounted to a rotating table
26
by adhesive means. The polishing pad
12
is applied to the wafer surface
22
at a specific pressure. The chemical mechanical polishing method can be used to provide a planar surface on dielectric layers, on deep and shallow trenches that are filled with polysilicon or oxide, and on various metal films. CMP polishing results from a combination of chemical and mechanical effects. A possible mechanism for the CMP process involves the formation of a chemically altered layer at the surface of the material being polished. The layer is mechanically removed from the underlying bulk material. An altered layer is then regrown on the surface while the process is repeated again. For instance, in metal polishing, a metal oxide may be formed and removed repeatedly.
A polishing pad is typically constructed in two layers overlying a platen with the resilient layer as the outer layer of the pad. The layers are typically made of polyurethane and may include a filler for controlling the dimensional stability of the layers. The polishing pad is usually several times the diameter of a wafer and the wafer is kept off-center on the pad to prevent polishing a non-planar surface onto the wafer. The wafer is also rotated to prevent polishing a taper into the wafer. Although the axis of rotation of the wafer and the axis of rotation of the pad are not collinear, the axes must be parallel. Polishing heads of the type described above used in the CMP process are shown in U.S. Pat. No. 4,141,180 to Gill, Jr., et al.; U.S. Pat. No. 5,205,082 to Shendon et al; and, U.S. Pat. No. 5,643,061 to Jackson, et al. It is known in the art that uniformity in wafer polishing is a function of pressure, velocity and the concentration of chemicals. Edge exclusion is caused, in part, by a non-uniform pressure applied on a wafer. The problem is reduced somewhat through the use of a retaining ring which engages the polishing pad, as shown in the Shendon et al patent.
Referring now to
FIG. 1C
, wherein an improved CMP head
20
, sometimes referred to as a Titan® head which differs from conventional CMP heads in two major respects is shown. First, the Titan® head employs a compliant wafer carrier and second, it utilizes a mechanical linkage (not shown) to constrain tilting of the head, thereby maintaining planarity relative to a polishing pad
12
, which in turn allows the head to achieve more uniform flatness of the wafer during polishing. The wafer
10
has one entire face thereof engaged by a flexible membrane
16
, which biases the opposite face of the wafer
10
into face-to-face engagement with the polishing pad
12
. The polishing head and/or pad
12
are moved relative to each other, in a motion to effect polishing of the wafer
10
. The polishing head includes an outer retaining ring
14
surrounding the membrane
16
, which also engages the polishing pad
12
and functions to hold the head in a steady, desired position during the polishing process. As shown in
FIG. 1C
, both the retaining ring
14
and the membrane
16
are urged downwardly toward the polishing pad
12
by a linear force indicated by the numeral
18
which is effected through a pneumatic system.
More detailed views of the Titan® head are shown in
FIGS. 2A and 2B
.
FIG. 2A
shows that in a Titan® head, two separate pressure chambers of a carrier chamber
30
and a membrane chamber
32
are used during a polish process. A carrier pressure
34
exerts on the retaining ring
14
, while a membrane pressure
18
translates into wafer backside pressure. The retaining pressure is a function of both the membrane pressure and the carrier pressure, for instance, P
RR
=2.039 P
CAR
−1.908 P
MEM
.
The operation of the Titan® head
20
can be shown in FIG.
2
B. The Titan® head
20
picks up a wafer
10
by forming a suction cup with its membrane
16
. A pressure is applied to the innertube
28
to force the membrane
16
downwardly onto the wafer
10
to ensure a good seal with the suction cup. A vacuum is thus applied to the membrane
16
to lift the wafer
10
. The innertube
28
has little effect on the process because it is pressurized to the same pressure as the membrane chamber
32
. During a polishing process, a pressure of approximately 5.2 psi is applied on the retaining ring which is higher than a pressure of approximately 4.5 psi that is applied on the membrane, i.e., on the wafer. The higher pressure applied on the retaining ring ensures that the wafer
10
is always retained in the retaining ring
14
. However, after repeated usage, the bottom surface
36
of the retaining ring may be worn out and the wafer
10
may slide out during a polishing process. When such defective condition occurs, the wafer may be severely damaged or even broken.
FIG. 3
is a cross-sectional view of the continuation of an actual Titan® head. Within a Titan® head
20
, three separate fluid chambers are utilized, i.e., a membrane chamber
38
, an innertube chamber
40
and a retaining ring chamber
42
. When a leakage occurs between either two of the three chambers, or between all three chambers, a “cross-talking” defect occurs which prevents either a pressure or a vacuum to reach its destination and causes a defective processing condition. For instance, when the vacuum is inadequate, the wafer may slip out and be scratched or broken. A leakage between chambers may further cause defects such as abnormal removal rate on the wafer surface or poo
Chen Wen-Ten
Lin Chung-Yang
Lu Fang-Lin
Yeh Kau-Po
Politzer Jay L.
Taiwan Semiconductor Manufactoring Company Ltd.
Tung & Associates
Williams Hezron
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