Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2000-03-30
2002-07-09
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S158000, C327S161000, C327S277000
Reexamination Certificate
active
06417714
ABSTRACT:
BACKGROUND OF THE INVENTION
A common method of generating clock signals in high-frequency systems, including microprocessors systems operating in the GHz frequency range, is to use a phase-locked-loop (PLL) or a delay-locked-loop (DLL). A typical DLL employs a variable delay block in which the delay time depends on a digital code applied to the delay block. DLLs are simple to design using a digital design methodology, but they do not provide good range, and they are susceptible to different types of noise. One noise source is jitter in the least significant bit (LSB) of the digital code around the lock condition. The LSB itself might not be uniform across the range of operation. If, for example, the DLL is nearing lock at a frequency where the LSB is large, the associated jitter will also be large. Compounding this problem is jitter caused by power supply voltage (Vcc) variations—particularly bad at low power supply voltages.
FIG. 1
shows a typical prior art delay cell that is based on transistor gate capacitance loading in the signal path. The delay is controlled by the control signal C
1
which connects the gate capacitance of MP
2
to the signal path through MP
1
when C
1
is high. Such “RC” delay cells take up considerable die area, and are difficult to design for small (<100 ps) delays.
Frequently, a cascade of delay cells are used as the delay block. That is, a series of delay cells are arranged so that the output of each delay cell serves as the input to the next delay cell.
FIG. 2
shows a prior art DLL in which the delay block includes a cascade of “n” delay cells such as those shown in FIG.
1
. The delay cells are controlled by a digital code that is represented by code signals C
1
, C
2
, . . . Cn from a counter which is incremented and decremented by an up/down control signal from a phase detector. A problem with the circuit of
FIG. 2
, however, is that the jitter from each of the cells sums cumulatively.
REFERENCES:
patent: 5336940 (1994-08-01), Sorrells et al.
patent: 5355037 (1994-10-01), Andresen et al.
patent: 5451894 (1995-09-01), Guo
patent: 6163219 (2000-12-01), Kanasugi
J. Christiansen, “An Integrated High Resolution CMOS Timing Generator Based on an Array of Delay Locked Loops,” IEEE JSSC, vol. 31, No. 7, pp. 952-957, Jul. 1996.
B. Razavi, “A Study of Phase Noise in CMOS Oscillators,” IEEE JSSC, vol. 31, No. 3, pp. 331-343, Mar. 1996.
Lance A. Glasser, Daniel W. Dobberpuhl, “The Design and Analysis of VLSI Circuits,” Addison-Wesley Publishing Company, pp. 281-283, 1985.
Biyabani Ahmed
Soumyanath Krishnamurthy
Inter Corporation
Marger Johnson & McCollom
Wells Kenneth B.
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