Electrical computers and digital processing systems: processing – Processing architecture – Vector processor
Reexamination Certificate
2005-01-11
2010-06-15
Chan, Eddie P (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
Vector processor
C712S005000, C712S004000, C712S029000
Reexamination Certificate
active
07739480
ABSTRACT:
A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a location identifier of the scalar value within the vector in the bits defining the mixed vector and scalar instruction. The scalar value can be used directly from the vector register without the need to load the scalar to a scalar register prior to executing the instruction. The scalar location identifier may be embedded in the secondary op code of the instruction, or the instruction may have dedicated bits for providing the location of the scalar within the vector.
REFERENCES:
patent: 4541046 (1985-09-01), Nagashima et al.
patent: 4713748 (1987-12-01), Magar et al.
patent: 4841438 (1989-06-01), Yoshida et al.
patent: 4875161 (1989-10-01), Lahti
patent: 4881168 (1989-11-01), Inagami et al.
patent: 4890220 (1989-12-01), Nakagawa et al.
patent: 4933839 (1990-06-01), Kinoshita et al.
patent: 5073970 (1991-12-01), Aoyama et al.
patent: 5201058 (1993-04-01), Kinoshita et al.
patent: 5226171 (1993-07-01), Hall et al.
patent: 5247691 (1993-09-01), Sakai
patent: 5255382 (1993-10-01), Pawloski
patent: 5261113 (1993-11-01), Jouppi
patent: 5299320 (1994-03-01), Aono et al.
patent: 5418973 (1995-05-01), Ellis et al.
patent: 5423051 (1995-06-01), Fuller et al.
patent: 5426754 (1995-06-01), Grice et al.
patent: 5430884 (1995-07-01), Beard et al.
patent: 5510934 (1996-04-01), Brennan et al.
patent: 5513366 (1996-04-01), Agarwal et al.
patent: 5517666 (1996-05-01), Ohtani et al.
patent: 5526504 (1996-06-01), Hsu et al.
patent: 5530881 (1996-06-01), Inagami et al.
patent: 5537538 (1996-07-01), Bratt et al.
patent: 5537606 (1996-07-01), Byrne
patent: 5561808 (1996-10-01), Kuma et al.
patent: 5572704 (1996-11-01), Bratt et al.
patent: 5574924 (1996-11-01), Yoshinaga et al.
patent: 5604909 (1997-02-01), Joshi et al.
patent: 5625834 (1997-04-01), Nishikawa
patent: 5632025 (1997-05-01), Bratt et al.
patent: 5638500 (1997-06-01), Donovan et al.
patent: 5659706 (1997-08-01), Beard et al.
patent: 5669013 (1997-09-01), Watanabe et al.
patent: 5673407 (1997-09-01), Poland et al.
patent: 5689653 (1997-11-01), Karp et al.
patent: 5734874 (1998-03-01), Van Hook et al.
patent: 5740402 (1998-04-01), Bratt et al.
patent: 5742277 (1998-04-01), Gossett et al.
patent: 5742842 (1998-04-01), Suetake et al.
patent: 5805875 (1998-09-01), Asanovic
patent: 5812147 (1998-09-01), Van Hook et al.
patent: 5838984 (1998-11-01), Nguyen et al.
patent: 5848286 (1998-12-01), Schiffleger et al.
patent: 5864703 (1999-01-01), Van Hook et al.
patent: 5884070 (1999-03-01), Panwar
patent: 5898882 (1999-04-01), Kahle et al.
patent: 5931945 (1999-08-01), Yung et al.
patent: 5933157 (1999-08-01), Van Hook et al.
patent: 5933650 (1999-08-01), Van Hook et al.
patent: 5938756 (1999-08-01), Van Hook et al.
patent: 5946496 (1999-08-01), Sugumar et al.
patent: 5954815 (1999-09-01), Joshi et al.
patent: 5982939 (1999-11-01), Van Hook
patent: 5991531 (1999-11-01), Song et al.
patent: 6006315 (1999-12-01), Park
patent: 6016395 (2000-01-01), Mohamed
patent: 6058465 (2000-05-01), Nguyen
patent: 6075906 (2000-06-01), Fenwick et al.
patent: 6098162 (2000-08-01), Schiffleger et al.
patent: 6105129 (2000-08-01), Meier et al.
patent: 6141673 (2000-10-01), Thayer et al.
patent: 6166748 (2000-12-01), Van Hook et al.
patent: 6167507 (2000-12-01), Mahalingaiah et al.
patent: 6170001 (2001-01-01), Hinds et al.
patent: 6571328 (2003-05-01), Liao
patent: 6857061 (2005-02-01), Liao et al.
patent: 7213131 (2007-05-01), Hansen et al.
patent: 2002/0130874 (2002-09-01), Baldwin
“Compiling collection-oriented languages onto massively parallel computers” Blelloch, Guy E. and Sabot, Gary W. (1988). Publisher: IEEE, pp. 575-585.
Intel “IA-64 Applicatoin Developers Architecture Guide”, May 1999, p. 7-27.
TMS32010 Users Guide, Digital Signal Processing Products, 1983, by Texas Instruments, p. 3-7.
Motorola Inc., “PowerPC Microprocessor Family: The Programming Environments”, 1994.
IBM, “PowerPC 740 and PowerPC 750 RISC Microprocessor Family User Manual”, 1998.
MIPS Technologies, Inc., Silicon Graphics Introduces Enhanced MIPS® Architecture to Lead the Interactive Digital Revolution—Future Digital Media Processors Will Enable New World of High-Performance and Low-Cost Interactive Digital Applications, 1996.
Web Extension I: Survey of RISC Architectures.
MIPS V Instruction Set.
MIPS Extention for Digital Media with 3D.
IEEE, “Subword Parallelism With MAX-2”, 1996.
Cheng Howard
Liao Yu-Chung C.
Sandon Peter A.
Van Hook Timothy J.
Alrobaye Idriss N
Chan Eddie P
Nintendo Co. Ltd.
Nixon & Vanderhye P.C.
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