Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Using particular code or particular counting sequence
Reexamination Certificate
2001-09-11
2004-03-09
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Systems
Using particular code or particular counting sequence
C377S027000, C377S028000
Reexamination Certificate
active
06704387
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to compact disk writing technology, and more specifically, to timing of a write-restart using bit counting.
BACKGROUND
A compact disk recorder writes data to a disc by using its laser to physically burn pits into the organic dye of the disc. When heated beyond a critical temperature, the area ‘burned’ becomes opaque (or absorptive) through a chemical reaction to the heat and subsequently reflects less light than areas that have not been heated by the laser. A CD-R (compact disk-recordable) or CD-RW (compact disk re-writable) can generally be used in a normal CD player as if it were a normal CD.
By mid-1998 drives were capable of writing at quad-speed and reading at twelve-speed (denoted as ‘4×/12×’) and were bundled with much improved CD mastering software. The faster the writing speed the more susceptible a CD-R writer is to buffer underruns—the most serious of all CD recording errors. A buffer underrun occurs when the system cannot keep up a steady stream of data as required by CD recording. The CD recorder has a buffer to protect against interruptions and slowdowns, but if the interruption is so long that the recorder's buffer is completely emptied, a buffer underrun occurs, writing halts, and most often the recordable CD is irretrievably damaged.
One prior art solution to this problem is to use multi-session CD-ROM drives. On multi-session CD-ROMs, while it is impossible to erase data—once a location on the CD-R disc has been written to, the color change is permanent—there may be multiple write sessions to different areas of the disc. This permits the recording to stop and restart. However, only multi-session compatible CD-ROM drives can read subsequent sessions; anything recorded after the first session will be invisible to older drives. This is disadvantageous, as it is not compatible with the millions of currently available drives.
A new solution to this problem is to use link-less restarting. This permits restarting without the linking area required by multi-session drives. Timing the location of the restart is difficult. Generally, in link-less restart, a particular starting location is identified, and bit counting is used to reach the starting location.
One issue with restarting a session is that the bit counting may be problematic. In the prior art, a 33.8688 MHz crystal is used to generate the EFCK (EFM Bit Clock) in CLV (constant linear velocity) mode. The EFCK is then used to control the WGATE on timing in the restart frame once ESFS (Encode Subcode Frame Sync) is synchronized with SCOR (Subcode Ready Sync) for the target frame. Because there are variations on the spindle motor speed during different read and write processes, counting to the restart bit using a fixed clock EFCK causes inconsistency on the WGATE on timing.
SUMMARY OF THE INVENTION
method and apparatus for providing of normalizing a bit count is provided. The method comprises counting bits for a first frame, and normalizing a target bit in a target frame using the bits of the frame. The method then comprises counting to the normalized target bit in the target frame.
REFERENCES:
patent: 6169973 (2001-01-01), Tsutsui et al.
Blakely , Sokoloff, Taylor & Zafman LLP
Oak Technology, Inc.
Wambach Margaret R.
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