Method and apparatus for non-speculative pre-fetch operation...

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

Reexamination Certificate

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C709S238000, C712S207000

Reexamination Certificate

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07042887

ABSTRACT:
A system is provided for enabling a non-speculative pre-fetch operation for processing instructions to be performed in the background ahead of immediate packet processing by a packet processor. The system comprises a packet-management unit for accepting data packets and en-queuing them for processing, a processor unit for processing the data packets, a processor core memory for holding context registers and functional units for processing, a memory for holding a plurality of instruction threads and a software-configurable hardware table for relating queues to pointers to beginnings of instruction threads. The packet-management unit selects an available context in the processor core for processing of a data packet, consults the table, and communicates the pointer to the processor, enabling the processor to perform the non-speculative pre-fetch for instructions.

REFERENCES:
patent: 4200927 (1980-04-01), Hughes et al.
patent: 4707784 (1987-11-01), Ryan et al.
patent: 4942518 (1990-07-01), Weatherford et al.
patent: 5023776 (1991-06-01), Gregor
patent: 5121383 (1992-06-01), Golestani
patent: 5291481 (1994-03-01), Doshi et al.
patent: 5408464 (1995-04-01), Jurkevich
patent: 5471598 (1995-11-01), Quattromani et al.
patent: 5559970 (1996-09-01), Sharma
patent: 5634015 (1997-05-01), Chang et al.
patent: 5659797 (1997-08-01), Zandveld et al.
patent: 5708814 (1998-01-01), Short et al.
patent: 5724565 (1998-03-01), Dubey et al.
patent: 5784649 (1998-07-01), Begur et al.
patent: 5784699 (1998-07-01), McMahon et al.
patent: 5796966 (1998-08-01), Simcoe et al.
patent: 5812810 (1998-09-01), Sager
patent: 5892966 (1999-04-01), Petrick et al.
patent: 5918050 (1999-06-01), Rosenthal et al.
patent: 5978570 (1999-11-01), Hillis
patent: 5978893 (1999-11-01), Bakshi et al.
patent: 5987578 (1999-11-01), Butcher
patent: 6009516 (1999-12-01), Steiss et al.
patent: 6016308 (2000-01-01), Crayford et al.
patent: 6023738 (2000-02-01), Priem et al.
patent: 6047122 (2000-04-01), Spiller
patent: 6070202 (2000-05-01), Minkoff et al.
patent: 6073251 (2000-06-01), Jewett et al.
patent: 6088745 (2000-07-01), Bertagna et al.
patent: 6131163 (2000-10-01), Wiegel
patent: 6151644 (2000-11-01), Wu
patent: 6157955 (2000-12-01), Narad et al.
patent: 6169745 (2001-01-01), Liu et al.
patent: 6219783 (2001-04-01), Zahir et al.
patent: 6223274 (2001-04-01), Catthoor et al.
patent: 6226680 (2001-05-01), Boucher et al.
patent: 6247105 (2001-06-01), Goldstein et al.
patent: 6249801 (2001-06-01), Zisapel et al.
patent: 6253313 (2001-06-01), Morrison et al.
patent: 6263452 (2001-07-01), Jewett et al.
patent: 6381242 (2002-04-01), Maher, III et al.
patent: 6453360 (2002-09-01), Muller et al.
patent: 6460105 (2002-10-01), Jones et al.
patent: 6502213 (2002-12-01), Bowman-Amuah
patent: 6523109 (2003-02-01), Meier
patent: 6529515 (2003-03-01), Raz et al.
patent: 6535905 (2003-03-01), Kalafatis et al.
patent: 6614796 (2003-09-01), Black et al.
patent: 6625808 (2003-09-01), Tarditi
patent: 6640248 (2003-10-01), Jorgensen
patent: 6738371 (2004-05-01), Ayres
patent: 6738378 (2004-05-01), Tuck, III et al.
patent: 6813268 (2004-11-01), Kalkunte et al.
patent: 2001/0004755 (2001-06-01), Levy et al.
patent: 2001/0005253 (2001-06-01), Komatsu
patent: 2001/0043610 (2001-11-01), Nemirovsky et al.
patent: 2001/0052053 (2001-12-01), Nemirovsky et al.
patent: 2002/0016883 (2002-02-01), Musoll et al.
patent: 2002/0049964 (2002-04-01), Takayama et al.
patent: 2002/0054603 (2002-05-01), Musoll et al.
patent: 2002/0071393 (2002-06-01), Musoll
patent: 2002/0083173 (2002-06-01), Musoll et al.
patent: 2002/0124262 (2002-09-01), Basso et al.
patent: 2004/0015598 (2004-01-01), Lin
patent: 2004/0148382 (2004-07-01), Narad et al.
patent: 2004/0172471 (2004-09-01), Porter
patent: 2004/0172504 (2004-09-01), Balazich et al.
patent: 2004/0213251 (2004-10-01), Tran et al.
patent: 2005/0061401 (2005-03-01), Tokoro et al.
patent: 2005/0066028 (2005-03-01), Illikkal et al.
patent: WO03005645 (2002-06-01), None
U.S. Appl. No. 09/737,375, Mario Nemirovsky et al.
U.S. Appl. No. 60/181,364, Mario Nemirovsky et al.
U.S. Appl. No. 491527, Nandakumar Sampath et al.
Knuth, Donald E., “The Art of Computer Programming, Third Edition, vol. 1, Fundamental Algorithms”, “Sec. 2.5 Dynamic Storage Allocation”, 1997, pp. 435-456, Addison-Wesley, US.
Diefendorff, Keith, K7 Challenges Intel, Microprocessor Report, Oct. 26, 1998, vol. 12, No. 14, US.
U.S. Appl. No. 09/608,750, Nemirovsky et al., Not published.
Melvin et al. “Extended Instruction Set for a Packet Processing Applications,” Jul. 5, 2001, Disclosure Document #496559.
Musoll et al, “Hardware Algorithm for Allocating and De-Allocating Consecutive Blocks of Memory,” Apr. 3, 2001, Disclosure Document #491557.
Musoll et al., “Mechanism to Overflow Packets to a Software Controlled Memory When They Do Not Fit into a Hardware Controlled Memeory,”, Jul. 3, 2001, Disclosure Document #496391.
Musoll et al., “Mechanism for Allowing a Limited Packet Head and/or Tail Growth Without Moving the Packet to a Different Memeory Location,” Apr. 16, 2001, Disclosure Document #492429.
Musoll et al., Mechanism to Activate a Context When No Stream is Running in a Multi-Streaming Processing Core,: Apr. 16, 2001, Disclosure Document #492431.
Musoll, Enrique, “Functional Validation of a Packet Management Unit,” May 18, 2001, Disclosure Docment #494011.
Yamamoto, Wayne,An Analysis of Multistreamed, Superscalar Processor Architectures.University of California Santa Barbara Dissertation. Dec. 1995. Santa Barbara, US.
Yamamoto et al. “Increasing Superscalar Performance Through Multistreaming.”Parallel Architectures and Compilation Techniques(PACT '95). 1995.
The PowerPC Architecture: A Specification for a New Family of RISC Processors, 2ndEd. May 1994. pp. 70-72. Morgan Kaufmann. San Francisco, US.
MC68020 32-Bit Microprocessor User's Manual. 3rdEd.. 1989. pp. 3-125, 3-126, and 3-127. Prentice Hall, NJ, US.
Potel, M. J. “Real-Time Playback in Animation Systems.”Proceedings of the 4thAnnual Conference on Computer Graphics and Interactive Techniques.1977. pp. 72-77. San Jose, CA, US.
ARM Architecture Reference Manual. 1996. pp. 3-41, 3-42, 3-43, 3-67, and 3-68. Prentice Hall, NJ, US.
ESA/390 Principles of Operation. IBM Online Publications Center Reference No. SA22-7201-08. Table of Contents and paras. 7.5.31 and 7.5.70. IBM Corporation, Boulder, CO, US.
MC88110 Second Generation RISC Microprocessor User's Manual. 1991. pp. 10-66, 10-67, and 10-71. Motorola, Inc.
Diefendorff, Keith et al. “Organization of the Motorola 88110 Superscalar RISC Microprocessor.”IEEE Journal of Microelectronics.Apr. 1992. pp. 40-63, vol. 12, No. 2, IEEE. New York, NY, US.
Kane, Gerry.PA-RISC 2.0 Architecture. 1996, pp. 7-106 and 7-107. Prentice Hall. NJ, US.
Diefendorff, Keith et al. “AltiVec Extension to PowerPC Accelerates Media Processing.”IEEE Journal of Microelectronics.vol. 20, No. 2 (2000): pp. 85-95.
Grunewald, Winfried et al. “Towards Extremely Fast Context Switching in a Block Multithreaded Processor.”Proceedings of EUROMICRO22, 1996. pp. 592-599.
Bradford, Jeffrey et al. “Efficient Synchronization for Multithreaded Processors.”Workshop on Multithreaded Execution, Architecture, and Compilation.Jan.-Feb. 1998. pp. 1-4.
Pai, Vijay et al. “An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors.”Proceedings of ASPLOS-VII, Oct. 1996: pp. 12-23, ACM, Inc.
Yoaz et al. “Speculation Techniques for Improving Load Related Instruction Scheduling.” 1999. pp. 42-53, IEEE.
Kessler, R. E. “The Alpha 21264 Microprocessor: Out-of-Order Execution at 600 MHz.” Aug. 1998.
Donalson et al. “DISC: Dynamic Instruction Stream Computer, An Evaluation of Performance.”26thHawaii Conference on Systems Sciences.vol. 1. 1993. pp. 448-456.
Nemirovsky et al. “DISC: Dynamic Instruction Stream Computer.” ACM. 1991. pp. 1

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