Electrolysis: processes – compositions used therein – and methods – Electrolytic coating – Coating selected area
Patent
1998-06-11
2000-10-17
Mayekar, Kishor
Electrolysis: processes, compositions used therein, and methods
Electrolytic coating
Coating selected area
205137, 205147, 205148, 205 87, C25D 502
Patent
active
061325864
ABSTRACT:
Plating of metal interconnections in semiconductor wafer manufacturing is performed by providing relative motion between a bipolar electrode assembly a single metallized surface of a semiconductor wafer without necessary physical contact with the wafer or direct electrical connection thereto.
REFERENCES:
patent: 4153531 (1979-05-01), Faul et al.
patent: 4430167 (1984-02-01), Inoue
patent: 5096550 (1992-03-01), Mayer et al.
patent: 5209833 (1993-05-01), Foell et al.
patent: 5256565 (1993-10-01), Bernhardt et al.
patent: 5344539 (1994-09-01), Shinogi et al.
patent: 5447615 (1995-09-01), Ishida
patent: 5486282 (1996-01-01), Datta et al.
patent: 5531874 (1996-07-01), Brophy et al.
patent: 5536388 (1996-07-01), Dinan et al.
patent: 5543032 (1996-08-01), Datta et al.
patent: 5567300 (1996-10-01), Datta et al.
patent: 5567304 (1996-10-01), Datta et al.
patent: 5575706 (1996-11-01), Tsai et al.
patent: 5591671 (1997-01-01), Kim et al.
patent: 5660706 (1997-08-01), Zhao et al.
patent: 5695810 (1997-12-01), Dubin et al.
A.F. Bernhardt, et al., "Electrochemical Planarization for Multi-Level Metallization of Microcircuitry," Circuitree pp. 41-46, Oct. 1995.
R.J. Contolini, et al., "Electrochemical Planarization for MultiLevel Metallization," J. Electrochem. Soc. 141 (9) :2503-2510, Sep.1994.
M.J. DeSilva and Y.S. Diamand, "A Novel Seed Layer Scheme to Protect Catalytic Surface for Eletroless Deposition," J. Electrochem. Soc. 143 (11) :3512-3516, Nov. 1996.
J.W. Dini, "Brush Plating: Recent Property Data," Metal Finishing pp. 89-93, Jun. 1997.
V.M. Dubin and Y.S. Diamand, "Selective and Blanket Electroless Copper Deposition for Ultralarge Scale Integration," J. Electrochem. Soc. 144(3):898-908, Mar. 1997.
C.W. Kaanta, et al., "Dual Damascene: A ULSI Wiring Technology," VMIC Conference, pp. 144-152, Jun. 1991.
J.G. Ryan, et al., "The Evolution of Interconnection Technology at IBM," IBM J. Res. & Dev. 39(4):1-9,, 1995, (no month available).
P. Singer, "Wafer Processing,"Semiconductor International pp. 40, Aug. 1997.
P. Singer, "Making the Move to Dual Damascene Processing," Semiconductor International pp. 79-81, Aug. 1997.
Adams John A.
Krulik Gerald A.
Smith Everett D.
Integrated Process Equipment Corporation
Mayekar Kishor
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