Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
1993-06-24
2004-04-27
Vigushin, John B. (Department: 2827)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S780000, C361S782000, C361S783000, C257S664000, C257S724000, C257S728000, C257S924000, C333S246000, C333S247000
Reexamination Certificate
active
06728113
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to the field of electronic and microelectronic packaging and, more particularly, to a multichip package, a method for assembling, testing and repairing systems so packaged, and a method for communicating between circuits so packaged, via capacitive coupling. Of particular interest are digital systems, meaning systems which contain important constituents that operate according to the rules of multistate or binary logic.
BACKGROUND OF THE INVENTION
Packaging Technology
Electronic systems are usually implemented as hierarchical packages of components. Passive or active electronic elements, such as resistors and transistors, and their wiring are typically combined into memory or logic units, which are then combined into circuits and devices, which are combined into larger functional units, and so forth up to the level of a system.
Each higher level of hierarchy grants the designer greater productivity, but compounds costs for connecting packages together logically and physically. Communication of data and timing among devices at each of these levels requires signal interconnection means, which the package provides. The package also provides powering means and fulfills other requirements such as physical support, heat removal and protection.
By convention, there are five hierarchical packaging levels 0-4, although these levels are not rigidly defined. An exemplary scale in the hardware system hierarchy is the naked semiconductor wafer, sometimes called an undiced “Level 0” package. Many components are formed simultaneously on a common substrate during fabrication stages, even if the substrate is subsequently separated into subunits. For instance, wiring, memory or logic gates may be assembled into integrated circuits on the surface of a semiconductor wafer and then cut into individual dies. Examples of dies include microelectronic devices implemented on semiconductor materials, superconductors bearing Josephson Junctions, and materials bearing other quantum interference devices.
Individual dies are typically mounted into “Level 1” packages, which provide mechanical stability, protection, cooling and heat dissipation, power and grounding, and interconnection of signal lines (including clocking) to other packages. Examples include DIP, ceramic, surface mounted and socketed packages.
A “Level 2” package is a module carrying one or more Level 1 or Level 0 packages and interconnecting their signal and power wiring. It typically comprises a printed circuit board (PCB), a printed wiring board (PWB), or a thermal conduction module, and may cluster one or more interconnected packages for these purposes. “Level 3” assemblies further organize the Level 1 and Level 2 packages, typically with backplanes, but do not differ conceptually from Level 2 or Level 1 packages. The “Level 4” package canonically ties together the lower level packages with power supplies, environmental systems, mechanical systems, peripherals, and so forth to provide system functionality.
A multichip module (a/k/a “MCM”) (also known as a “Level 1½” package) provides modular functionality as a Level 2-like or Level 3-like package for holding and interconnecting multiple dies and/or associated interconnections. At a minimum, an MCM provides the signal distribution, and power is usually distributed by way of the MCM as well. The MCM may also or merely encapsulate its constituent dies as an erstwhile Level 1 or Level 0 package, thereby providing protection. It may also communicate the dies to a heat sinking substrate, thereby providing heat dissipation.
Strictly speaking, an MCM could be treated as a package at any level of hierarchy, as defined in practice by its interconnection topology. Note that the term “chip” is used interchangeably in the industry both in reference to Level 0 dies and Level 1 packages (e.g., a multichip module is usually in fact a multidie module). As used herein, the term chip refers to a Level 0 package or die unless context indicates otherwise. The term “module” or “submodule” as used herein is intended to be general, and can refer to any package level, for example one or more Level 0 dies, one or more Level 1 or Level 0 chips (packaged or not), and of course higher order ensembles.
Present MCM Technologies
An MCM involves two or more dies, whether bare or encapsulated, mounted and conductively coupled to it. It provides power and inter-die signal wiring. In some MCM technologies, the dies are physically bonded to a substrate, and leads that are wire-bonded to peripherally positioned contacts (e.g., pins) supply the conductive connections between the dies and a multichip substrate. Other technologies utilize a “flip-chip” configuration in which the leads of the dies are positioned either peripherally or over much of the die area (such as a pin grid array (PGA) or solder bumps) and are soldered or otherwise bonded to respective contacts on the multichip substrate.
Several families of multichip packaging technology are standard at present. The so-called MCM-L technology utilizes a laminated, organic board substrate to which dies are bonded by flip-chip, tape automatic bonding (TAB), or wire-bonding. In the MCM-C technologies, dies are attached either directly by flip-chip or indirectly in prepackaged carriers to a ceramic thick-filmed substrate. The ceramic substrate is formed either sequentially, by a print and fire process, or by lamination and sequential co-insertion of screened green sheets. The MCM-D technology utilizes deposited thin-film substrates to which dies are then attached as in MCM-C. There are also variations of these three basic MCM technologies. For example, a variation using plastic packages and involving molding compounds and lead frames is the so-called multichip plastic quad packs (MCM-P) technology. Another recent variation involves the use of deposited thin films on a ceramic multichip substrate, referred to alternatively as MCM-DC or MCM-CD, and typically provides inter-die signal wiring in the deposited polymer-metal thin-film layers and power/ground wiring in the co-fired ceramic thick-filmed substrate. All of these technologies are subjects of intense research and invention in industry and universities. (See Rao R. Tummala, “Multichip Packaging—A Tutorial.”
Proc. of the IEEE
, December, 1992.)
Many approaches to the construction of high density multichip modules have been proposed. The IBM C4 technology attaches dies to the multichip module in a flip-chip face-down configuration. The arrangement minimizes the parasitic inductance of the package leads, and allows pad location at any point on the interior of the die. Typically, dies are attached to the module using a reflow-solder approach. Dies are bumped by bonding to each pad several layers of protective metalization followed by a 10-200 micron diameter solder ball. A plurality of dies are then accurately positioned on the multichip module, and reflow-soldered into place. Inspection of the solder joints can be done with thermographic or radiographic techniques, but may be difficult otherwise. Pad location is no longer limited to the die periphery, but is often constrained by thermal coefficient of expansion mismatch between silicon and module to lie within some radius of the center of the die. Repair is carried out by module heating, die removal, and reflow-soldering of replacement die.
“Chips-first” face-up wire-bonding of silicon dies to high density silicon, ceramic, or copper-polyimide modules is similar to conventional hybrid manufacturing technologies, and shares difficulties in rework and bonding yield. The GE/TI process forms a planar wafer-like module from collections of selected loose dies placed face down on a flat surface, and then encapsulates it in a polyimide carrier. After curing, this carrier is flipped over, planarized, and used as a module for further (possibly multilayer) metalization. The major advantages of metalizing on top of planar ensembles of dies include the fine lithography achievable and very small interconnect parasitics.
Knight Thomas F.
Salzman David B.
Pennie & Edmonds LLP
Polychip, Inc.
Vigushin John B.
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